ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 17

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.5
Holdover accuracy is defined as the absolute frequency accuracy of an output clock signal, when it is not locked to
an external reference signal, but is operating using storage techniques. For the ZL30108, the storage value is
determined while the device is in Normal Mode and locked to an external reference signal.
6.6
Also referred to as pull-in range. This is the input frequency range over which the PLL must be able to pull into
synchronization. The ZL30108 capture range is equal to
For example, a +32 ppm master clock results in a capture range of +162 ppm on one side and -98 ppm on the other
side of frequency range.
6.7
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the ZL30108.
6.8
TIE is the time delay between a given timing signal and an ideal timing signal.
6.9
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
6.10
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode
change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to
a steady state.
6.11
This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
•
•
•
•
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. See Section 8.2, “Performance Characteristics“ for Maximum Phase Lock Time.
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
in-lock phase distance
Holdover Accuracy
Capture Range
Lock Range
Time Interval Error (TIE)
Maximum Time Interval Error (MTIE)
Phase Lock Time
Phase Continuity
Zarlink Semiconductor Inc.
ZL30108
17
±
130 ppm minus the accuracy of the master clock (OSCi).
Data Sheet