ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 12

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.4
The DPLL of the ZL30108 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled
oscillator as shown in Figure 8. The data path from the phase detector to the filter is tapped and routed to the lock
indicator that provides a lock indication which is output at the LOCK pin.
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the loop filter circuit.
Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz, suitable to provide timing
and synchronization for SONET/SDH network interface cards.
Digital Phase Lock Loop (DPLL)
TIE corrector circuit
virtual reference
from
Detected REF Frequency
16.384 MHz, 19.44 MHz
2.048 MHz, 8.192 MHz,
8 kHz, 1.544 MHz,
Table 1 - Loop Filter Bandwidth Settings
2 kHz
detector
phase
Figure 8 - DPLL Block Diagram
Zarlink Semiconductor Inc.
ZL30108
control state machine
state select from
12
loop filter
Loop Filter Bandwidth
14 Hz
29 Hz
controlled
oscillator
indicator
digitally
lock
feedback signal from
frequency select MUX
frequency synthesizer
LOCK
DPLL reference to
Data Sheet