ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 10

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.3
The TIE Corrector Circuit eliminates phase transients on the output clock that may occur in the course of recovery
from Automatic Holdover mode to Normal mode.
On recovery from Automatic Holdover mode or when switching to another reference input, the TIE corrector circuit
measures the phase delay between the current phase (feedback signal) and the phase of the selected reference
signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that
is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase
transient it experiences when it switches to another reference input or recovers from Automatic Holdover mode.
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 14 and Figure 15. The speed of the phase alignment correction is limited by the loop filter bandwidth.
Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case
the output clocks will always align with the selected input reference. This is illustrated in Figure 7.
Time Interval Error (TIE) Corrector Circuit
+20 ppm
-20 ppm
C20i Clock Accuracy
0 ppm
-100
Figure 6 - Out-of-Range Thresholds for OOR_SEL=0
-75
-72
-60
-52
-50
-40
-32
Zarlink Semiconductor Inc.
C20
-32
-25
-20
ZL30108
C20
0
0
10
20
C20
20
25
32
40
50
52
60
72
75
100
In Range
In Range
Out of Range
In Range
Frequency offset [ppm]
Out of Range
Out of Range
Data Sheet