ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 13

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30108.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In the Automatic Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was
generating in Normal Mode. The frequency in the Automatic Holdover mode is calculated from frequency samples
stored 26 ms to 52 ms before the ZL30108 entered the Automatic Holdover mode. This ensures that the coarse
frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the
holdover frequency.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL goes into the Automatic Holdover mode, the
LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in the Automatic Holdover mode, the LOCK
pin will go low. In Freerun mode the LOCK pin will go low immediately.
4.5
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of the input references (REF0 or REF1).
The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping
techniques to minimize the output jitter. The clock and frame pulse outputs have limited drive capability and should
be buffered when driving high capacitance loads.
4.6
As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30108 is based on the input MODE_SEL.
4.7
The ZL30108 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Frequency Synthesizers
State Machine
Master Clock
Zarlink Semiconductor Inc.
ZL30108
13
Data Sheet