ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet - Page 18

• Manufacturer Part Number: ZL30108LDE1
• Description: SONET/SDH Network Interface DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.0
This section contains ZL30108 application specific details for power supply decoupling, clock and crystal operation,
reset operation,and control operation.
7.1
Jitter levels on the ZL30108 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30108 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
7.2
The ZL30108 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30108.
7.2.1
When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30108 and the OSCo
output should be left open as shown in Figure 10.
Power Supply Decoupling
Master Clock
Applications
Clock Oscillator
1
2
3
4
Table 5 - Typical Clock Oscillator Specification
Frequency
Tolerance
Rise & Fall Time
Duty Cycle
ZL30108
Figure 10 - Clock Oscillator Circuit
OSCo
OSCi
No Connection
Zarlink Semiconductor Inc.
ZL30108
20 MHz OUT
18
+3.3 V
+3.3 V
GND
20 MHz
As required
<10 ns
40% to 60%
0.1 µF
Data Sheet