XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 29

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XR16L651CM

Manufacturer Part Number
XR16L651CM
Description
2.25V TO 5.5V UART WITH 32-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet

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REV. 1.3.0
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1).
These 2 bits are used to set the trigger level for the receiver FIFO interrupt.
selections..
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
4.6
B
FCR
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = DMA Mode disabled (default).
Logic 1 = DMA Mode enabled.
IT
0
0
1
1
-7
T
Line Control Register (LCR) - Read/Write
ABLE
B
FCR
IT
0
1
0
1
-6
10: T
B
FCR
IT
RANSMIT AND
0
0
1
1
-5
BIT
FCR
0
1
0
1
-4
BIT-1
R
0
0
1
1
ECEIVE
T
T
RIGGER
RANSMIT
16
24
30
8
FIFO T
L
EVEL
INT
BIT-0
0
1
0
1
RIGGER
29
T
R
RIGGER
L
See “DMA Mode” on page 11.
ECEIVE
EVEL
16
24
28
8
W
Table 10
L
S
ORD LENGTH
5 (default)
INT
EVEL
ELECTION WITH AUTO
2.25V TO 5.5V UART WITH 32-BYTE FIFO
6
7
8
below shows the selections. EFR bit-4
D
A
E
UTO
-
ASSERT
16
24
28
28
Table 10
RTS
RTS
shows the complete
HYSTERESIS
R
A
E
UTO
-
XR16L651
ASSERT
16
24
0
8
RTS

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