XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 15

• Manufacturer Part Number: XR16L651CM
• Description: 2.25V TO 5.5V UART WITH 32-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

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REV. 1.3.0
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including a start bit, data bits,
parity bit and stop bit(s). The least-significant-bit (Bit-0) is the first data bit to go out. The THR is the input
register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
F
2.9.1
2.9.2
2.9.3
IGURE
IGURE
9. T
10. T
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Flow Control Characters
16X Clock
O
16X Clock
O
PERATION IN NON
PERATION IN
Data
Byte
Data Byte
Transmit
Transmit Shift Register (TSR)
FIFO
-FIFO M
Transmit
Register
Holding
Transmit Data Shift Register
(THR)
AND
F
ODE
LOW
Transmit
FIFO
(TSR)
15
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
2.25V TO 5.5V UART WITH 32-BYTE FIFO
M
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becom es
empty. FIFO is Enabled by FCR
bit-0=1
ODE
M
S
B
TXNOFIFO1
L
S
B
T XF IF O 1
XR16L651