XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 17

• Manufacturer Part Number: XR16L651CM
• Description: 2.25V TO 5.5V UART WITH 32-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

áç
áç
REV. 1.3.0
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (logic 1) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level
level below the programmed trigger level. However, even under these conditions, the 651 will continue to
accept data until the receive FIFO is full if the remote UART transmitter continues to send data.
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see
With the Auto CTS function enabled, the UART will suspend transmission as soon as the stop bit of the
character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS# input is
re-asserted (logic 0), indicating more data may be sent.
áç
áç
F
2.11
2.12
IGURE
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS output pin (MCR bit-1 to logic 1 after it is enabled).
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin is de-asserted (logic 1) during Auto RTS flow control mode: ISR bit-5 will be set to logic 1.
Enable auto CTS flow control using EFR bit-7.
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1) during Auto CTS flow control mode: ISR bit-5 will be set to 1.
(See Table
Receive Data
Byte and Errors
12. R
Automatic RTS (Hardware) Flow Control
Auto CTS Flow Control
32 bytes by 11-bit
16X Clock
wide FIFO
ECEIVER
10). The RTS# output pin will be asserted again after the FIFO is unloaded to the next trigger
O
PERATION IN
Receive Data Shift
Figure
Register (RSR)
Data FIFO
Receive
Receive
13):
FIFO
Data
AND
A
Validation
Data falls to
UTO
Data Bit
Data fills to
Trigger=16
Example
FIFO
- RX FIFO trigger level selected at 16 bytes
24
8
RTS F
17
:
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
Figure
C
2.25V TO 5.5V UART WITH 32-BYTE FIFO
ONTROL
13):
M
ODE
Receive Data Characters
RXFIFO1
XR16L651