XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 25

• Manufacturer Part Number: XR16L651CM
• Description: 2.25V TO 5.5V UART WITH 32-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

áç
áç
áç
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REV. 1.3.0
See “Receiver” on page 16.
See “Transmitter” on page 14.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register.
When the receive FIFO (FCR bit-0 = a logic 1) and receive interrupts (IER bit-0 = logic 1) are enabled, the RHR
interrupts (see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR bit-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
T
A
4.3.1
A2-A0
ABLE
DDRESS
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
8: UART CONFIGURATION REGISTERS DESCRIPTION.
Receive Holding Register (RHR) - Read-Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
IER versus Receive FIFO Interrupt Mode Operation
XOFF1
XOFF2
DREV
XON1
XON2
N
DVID
DLM
EFR
R
DLL
AME
EG
RD/WR
RD/WR
R
W
R/W
R/W
R/W
R/W
R/W
RD
RD
EAD
RITE
/
Enable
B
Bit-7
Bit-7
Bit-7
Auto
CTS
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
Enable
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Auto
RTS
IT
0
-6
Baud Rate Generator Divisor
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
25
IRPW[7:0]
FCR[5:4],
MCR[7:5]
IER [7:4],
ISR [5:4],
MSR[7:4]
XFR[7:0]
B
Enable
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
-4
B
Bit-3
Bit-3
Bit-3
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
2.25V TO 5.5V UART WITH 32-BYTE FIFO
Cntl
IT
0
S
-3
HADED BITS ARE ENABLED WHEN
B
Bit-2
Bit-2
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
1
-2
B
Soft-
ware
Bit-1
Bit-1
Bit-1
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
0
-1
B
ware
Bit-0
Bit-0
Bit-0
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
IT
0
-0
EFR B
LCR
LCR
DLM=0x00
LCR=0xBF
LCR[7] = 1
DLL=0x00
XR16L651
C
LCR[7]=1
OMMENT
IT
0xBF
0xBF
-4=1.