XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 14

• Manufacturer Part Number: XR16L651CM
• Description: 2.25V TO 5.5V UART WITH 32-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
O
2.9
UTPUT
MCR Bit-7=1
115.2k
230.4k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
F
IGURE
T
ABLE
X T A L1
X T A L2
O
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
UTPUT
Table 4
8. B
4: T
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
AUD
400
Data Rate
shows the standard data rates available with a 14.7456 MHz crystal or external
R
C rystal
B uffer
O sc/
ATE
G
Clock (Decimal)
D
ENERATOR
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
D ivide by 4
D ivide by 1
P rescaler
P rescaler
16x
14.7456 MH
D
14
IVISOR FOR
Clock (HEX)
M C R B it-7=0
M C R B it-7=1
900
180
(default)
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
B aud R ate
D LL and D LM
G enerator
R egisters
Logic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
R ate C lock to
T ransm itter
S am pling
V
16X
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
áç
áç
áç
áç
D
E
ATA
REV. 1.3.0
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)