XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet
XR16L651CM
Available stocks
Related parts for XR16L651CM
XR16L651CM Summary of contents
Page 1
JANUARY 2004 GENERAL DESCRIPTION 1 The XR16L651 (651 2.25 to 5.5 volt Universal Asynchronous Receiver and Transmitter (UART) with 5 volt tolerant inputs. This device supports Intel and Motorola data bus interfaces and is software compatible to industry ...
Page 2
... Intel Bus Mode with IM# tied to GND and PCMODE# tied to VCC ORDERING INFORMATION ART UMBER XR16L651CM 48-Lead TQFP XR16L651IM 48-Lead TQFP MODE AS# VCC TXRDY# A9 DDIS# ...
Page 3
REV. 1.3.0 PIN DESCRIPTIONS AME IN YPE 16 (Intel (Motorola) MODE DATA BUS INTERFACE. The PCMODE# pin is connected to VCC ...
Page 4
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO AME IN CS0 9 CS1 10 CS2# 11 INT 30 (INT#) AS# 24 TXRDY# 23 RXRDY Mode Interface Signals. Connect PCMODE# pin to GND and IM# ...
Page 5
REV. 1.3 AME IN YPE AEN IRQA 30 O IRQB 29 IRQC 23 LPT1 LPT2 MODEM OR SERIAL I/O INTERFACE TX ...
Page 6
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO AME IN YPE XTAL1 14 XTAL2 15 O RCLK 5 BAUDOUT PCMODE# 36 DDIS ENIR 13 RESET 35 (RESET#) IM# 37 OP1 ...
Page 7
REV. 1.3.0 1.0 PRODUCT DESCRIPTION The XR16L651 (651 industry first multi-voltage UART that can operate from 2.25V to 5.5V power supplies. Its inputs are 5V tolerant to facilitate interconnection to transceiver devices of RS-232, ...
Page 8
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Host Data Bus Interface The host interface is 8 data bits wide with 3 address lines and control signals to execute bus read and write transactions. The 651 ...
Page 9
REV. 1.3 XR16L651 M IGURE ...
Page 10
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.1.1 PC MODE The PC mode interface includes an on-chip address decoder and interrupt selection function for the standard PC COM 1-4 port addresses. The selection is made through three input signals: ...
Page 11
REV. 1.3.0 2.2 5-Volt Tolerant Inputs The 651 can acccept inputs even when operating at 3.3V or 2.5V. But note that if the 651 is operating at 2.5V, its V may not be ...
Page 12
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.6 Interrupt The output function of interrupt, INT, output changes according to the operating bus type and various factors. Table 3 summarizes its behavior in Intel, Motorola and PC mode of operation. ...
Page 13
REV. 1.3.0 2.7 Crystal Oscillator or External Clock The 651 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in the UART. XTAL1 is the ...
Page 14
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO IGURE AUD ATE C rystal sc uffer Programming the Baud Rate Generator Registers DLM and DLL provides the ...
Page 15
REV. 1.3.0 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to ...
Page 16
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.10 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for ...
Page 17
REV. 1.3 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 32 bytes by 11-bit wide FIFO Receive Data Byte and Errors 2.11 Automatic RTS (Hardware) Flow Control Automatic RTS ...
Page 18
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO F 13. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# ...
Page 19
REV. 1.3.0 In the event that the receive buffer is overfilling and flow control needs to be executed, the 651 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. ...
Page 20
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.16 Infrared Mode The 651 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates the infrared mode. Activating the ...
Page 21
REV. 1.3.0 2.17 Sleep Mode & Wake-up Indicator The 651 is designed to operate with low power consumption. A special sleep mode is included to further reduce power consumption when the chip is not being used. ...
Page 22
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 2.18 Internal Loopback The 651 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...
Page 23
REV. 1.3.0 3.0 UART CONFIGURATION REGISTERS The 651 has a set of configuration registers selected by address lines A0 to A2. The based page registers are 16C550 compatible with EXAR enhanced feature registers located on the ...
Page 24
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO T 8: UART CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR ...
Page 25
REV. 1.3 UART CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit-7 ...
Page 26
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L651 in the FIFO polled mode of operation. ...
Page 27
REV. 1.3.0 IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) Logic 0 = Disable the CTS# interrupt (default). Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition ...
Page 28
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
Page 29
REV. 1.3.0 FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. Logic transmit FIFO reset (default). Logic 1 = Reset the transmit FIFO pointers and FIFO level ...
Page 30
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of the stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and ...
Page 31
REV. 1.3.0 LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. Logic 0 = Data registers are selected (default). Logic 1 = Divisor latch registers are selected if 4.7 Modem Control Register (MCR) or ...
Page 32
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO MCR[6]: Infrared Encoder/Decoder Enable Logic 0 is the default unless the IR mode is forced by the ENIR pin. This bit can overwrite the ENIR state after a power up or reset. ...
Page 33
REV. 1.3.0 LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit ...
Page 34
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO XFR [4]: Xon-Any Enable This bit enables and disables the Xon-Any function when Xon/Xoff software flow control is enabled. Logic 0 = Disable the Xon-Any function. Logic 1 = Enable the Xon-Any ...
Page 35
REV. 1.3.0 MSR[6]: RI Input Status RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The ...
Page 36
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 EFR BIT BIT ...
Page 37
REV. 1.3.0 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated (if IER ...
Page 38
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR XFR MSR IRPW SPR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# DTR# OP1# OP2# TXRDY# RXRDY# INT (16 Mode) ...
Page 39
REV. 1.3.0 Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (7x7x1 mm 48-TQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED TO 5. ...
Page 40
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO T ABLE XR16L651 Sink Current Chart 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 14: XR16L651 VOL S C INK URRENT VOL ...
Page 41
REV. 1.3.0 T ABLE XR 16L651 Source C urrent C hart 2.25V TO 5.5V UART WITH 32-BYTE FIFO 15: XR16L651 VOH S ...
Page 42
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator Frequency OSC External Clock Frequency ...
Page 43
REV. 1.3.0 AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER T Delay from AS# to IOW# WR1 T Data Setup Time (16 Mode, ...
Page 44
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER T Delay From Stop To Interrupt SI T Delay From Initial ...
Page 45
REV. 1.3 IGURE ODEM NPUT UTPUT IOW# Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ODE NTEL ATA ...
Page 46
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO F 19 IGURE ODE NTEL ATA A0- Valid A2 Address T AS CS2# CS1 CS0 IOW# IOW D0-D7 Note: Only one chipselect and one write strobe should ...
Page 47
REV. 1.3 IGURE ODE NTEL ATA T AS# T AS1 A0-A2 Address T CS1 CS2# CS0 or CS1 T WR1 IOW# IOW D0-D7 Note: Only one chipselect and one ...
Page 48
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO F 23 IGURE ODE OTOROLA A0-A2 T ADS CS# T RWS R/W# D0- IGURE ATA US EAD IMING IN A0-A9 Address ...
Page 49
REV. 1.3 IGURE ATA US RITE IMING IN A0-A9 Address T AS3 AEN# T WR2 IOW# T DS3 D0- & I IGURE ECEIVE EADY NTERRUPT RX ...
Page 50
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO F 27 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into ...
Page 51
REV. 1.3 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX S D0:D7 S D0:D7 INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# ...
Page 52
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO F 31 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0: D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) ...
Page 53
REV. 1.3.0 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
Page 54
XR16L651 2.25V TO 5.5V UART WITH 32-BYTE FIFO REVISION HISTORY Date Revision January 2001 P1.0.0 Initial Datasheet. March 2001 P1.0.1 Corrected Package Dimensions table. April 2001 P1.0.2 Added the V May 2001 P1.0.3 Replaced TBD’s in Electrical Characteristics Tables. Added ...
Page 55
REV. 1.3.0 GENERAL DESCRIPTION................................................................................................. 1 F .................................................................................................................................................. 1 EATURES A ............................................................................................................................................. 1 PPLICATIONS ..................................................................................................................................................................... 1 IGURE LOCK IAGRAM IGURE NTEL OTOROLA AND MODE ............................................................................................................................. 2 ORDERING ...
Page 56
XR16L651 2.25V TO 5.5V DUART WITH 32-BYTE FIFO 4 RANSMIT OLDING EGISTER 4 NTERRUPT NABLE EGISTER 4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 25 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation .................................................................... ...