XR16L651CM EXAR [Exar Corporation], XR16L651CM Datasheet - Page 18

• Manufacturer Part Number: XR16L651CM
• Description: 2.25V TO 5.5V UART WITH 32-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
When software flow control is enabled
characters with the programmed Xon or Xoff-1,2 character value(s). If received character(s) (RX) match the
programmed values, the 651 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character values, the 651 will monitor
the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 651 will resume
operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters
selected, the 651 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
F
2.13
IGURE
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
13. A
Auto Xon/Xoff (Software) Flow Control
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
TXB
INTA
Trigger Reached
UTO
Receiver FIFO
Trigger Level
Local UART
(See Table
Transmitter
Auto CTS
Auto RTS
UARTA
Monitor
RTS
Data Starts
Receive
AND
Data
Assert RTS# to Begin
12) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
1
CTS F
2
Transmission
Trigger Level
3
4
RX FIFO
LOW
RTSA#
TXA
CTSA#
RXA
ON
ON
C
(See Table
ONTROL
5
O
7
Threshold
RTS High
PERATION
12), the 651 compares one or two sequential receive data
18
6
8
OFF
Suspend
OFF
RTSB#
CTSB#
Threshold
RTS Low
RXB
TXB
Restart
9
10
11
Trigger Reached
Remote UART
ON
Trigger Level
Receiver FIFO
12
Auto CTS
Auto RTS
Transmitter
UARTB
Monitor
ON
Trigger Level
RX FIFO
áç
áç
áç
áç
R T S C T S 1
REV. 1.3.0