XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 9

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
The 2850 includes an on-chip oscillator (XTAL1 and
XTAL2) to produce a clock for both UART sections in
the device. The CPU data bus does not require this
clock for bus operation. The crystal oscillator provides
a system clock to the Baud Rate Generators (BRG)
section found in each of the UART. XTAL1 is the input
to the oscillator or external clock buffer input with
XTAL2 pin being the output. For programming details,
see “Programmable Baud Rate Generator.”
MP
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance
load, ESR of 20-80 ohms and 100ppm frequency tol-
erance) connected externally between the XTAL1 and
XTAL2 pins (see Figure 4). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom
INTA/B Pin 0 = no data
2.8 C
T
ABLE
F
RYSTAL
IGURE
4: INTA
(FIFO D
1 = 1 byte
FCR B
22-47 pF
XTAL1
4. T
C1
O
SCILLATOR OR
IT
ISABLED
YPICAL OSCILLATOR CONNECTIONS
AND
-0 = 0
R
INTB P
ECEIVER
R2
)
22-47 pF
XTAL2
0 = FIFO below trigger level
1 = FIFO above trigger level
C2
Y1
3.3V AND 5V DUART WITH 128-BYTE FIFO
IN
E
(FIFO E
O
FCR B
XT
1.8432 MHz
(Optional)
PERATION
0-120
24 MHz
. C
R1
to
LOCK
IT
NABLED
-0 = 1
I
NPUT
F
OR
)
9
rates. Typical oscillator connections are shown in
Figure 4. For further reading on oscillator circuit
please see application note DAN108 on EXAR’s web
site.
A single Baud Rate Generator (BRG) is provided for
the transmitter and receiver, allowing independent
TX/RX channel control. The programmable Baud
Rate Generator is capable of operating with a crystal
frequency of up to 24 MHz. However, with an external
clock input on XTAL1 pin and a 2K ohms pull-up re-
sistor on XTAL2 pin (as shown in Figure 5) it can ex-
tend its operation up to 50 MHz (3.125 Mbps serial
data rate) at room temperature and 5.0V.
Each UART also has their own prescaler along with
the BRG. The prescaler is controlled by CLKSEL
hardware pin or a software bit in the MCR register.
The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4 and can
override the CLKSEL pin following reset. The clock
output of the prescaler goes to the BRG. The BRG
further divides this clock by a programmable divisor
between 1 and (2
clock of the serial data rate. The sampling rate clock
is used by the transmitter for data bit shifting and re-
ceiver for data sampling.
2.9 P
F
E
IGURE
XTENDED
ROGRAMMABLE
vcc
gnd
5. E
External Clock
D
XTERNAL
ATA
16
-1) to obtain a 16X sampling rate
R
R1
2K
B
ATE
VCC
AUD
C
LOCK
R
ATE
XTAL1
XTAL2
C
G
ONNECTION FOR
ENERATOR