XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 28

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

This register controls the XR16C2850 new functions
that are not available in ST16C550 or ST16C650A.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware
flow control application. After reset, these bits are set
to “0” to select the next trigger level for hardware flow
control. See Table 13 on page 27 for more details.
FCTR[2]: IrDa RX Inversion
• Logic 0 = Select RX input as encoded IrDa data
• Logic 1 = Select RX input as inverted encoded IrDa
FCTR[3]: Auto RS-485 Direction Control
• Logic 0 = Standard ST16C550 mode. Transmitter
• Logic 1 = Enable Auto RS485 Direction Control
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 10 on page 23 for more details.
4.18 F
(Idle state will be logic 0).
data (Idle state will be logic 1).
generates an interrupt when transmit holding regis-
ter becomes empty and transmit shift register is
shifting data out.
function. The direction control signal, RTS# pin,
changes its output logic state from low to high one
bit time after the last stop bit of the last character is
shifted out. Also, the Transmit interrupt generation
is delayed until the transmitter shift register
becomes empty. The RTS# output pin will automat-
ically return to a logic low when a data byte is
loaded into the TX FIFO.
FCTR
B
IT
0
0
1
1
-5
W
EATURE
RITE
T
ABLE
FCTR
B
IT
0
1
0
1
-4
14: T
C
ONTROL
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
RIGGER
R
EGISTER
T
3.3V AND 5V DUART WITH 128-BYTE FIFO
ABLE
T
ABLE
S
(FCTR) - R
ELECT
EAD
/
28
FCTR[6]: Scratchpad Swap
• Logic 0 = Scratch Pad register is selected as gen-
• Logic 1 = FIFO Count register (Read-Only),
FCTR[7]: Programmable Trigger Register Select
• Logic 0 = Registers TRG and FC selected for RX.
• Logic 1 = Registers TRG and FC selected for TX.
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 15). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Cau-
tion: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (dis-
able) before programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters soft-
ware flow control is supported. Combinations of soft-
ware flow control can be selected by programming
these bits.
4.19 E
eral read and write register. ST16C550 compatible
mode.
Enhanced Mode Select Register (Write-Only).
Number of characters in transmit or receive FIFO
can be read via scratch pad register when this bit is
set. Enhanced Mode Select Register is selected
when it is written into.
NHANCED
F
EATURE
R
EGISTER
(EFR)
XR16C2850
REV. 2.0.0