XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 25

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be
used for automatic hardware flow control by enabled
by EFR bit-6. If the modem interface is not used, this
output may be used as a general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 2850.
But it is available for use during Internal Loopback
Mode. In the Loopback Mode, this bit is used to write
the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, in-
terrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
• Logic 0 = INT (A-B) outputs disabled (three state
• Logic 1 = INT (A-B) outputs enabled (active mode)
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loop-
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550
• Logic 1 = Enable Xon-Any function. In this mode,
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and
• Logic 1 = Enable infrared IrDA receive and transmit
mode) and OP2# output set to a logic 1 (default).
and OP2# output set to a logic 0.
back section and Figure 13.
compatibility, default).
any RX character received will resume transmit
operation. The RX character will be loaded into the
RX FIFO , unless the RX character is an Xon or
Xoff character and the 2850 is programmed to use
the Xon/Xoff flow control.
transmit input/output interface. (Default)
inputs/outputs. The TX/RX output/input are routed
to the infrared encoder/decoder. The data input and
output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX
output will be a logic 0 during idle data conditions.
3.3V AND 5V DUART WITH 128-BYTE FIFO
25
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the
• Logic 1 = Divide by four. The prescaler divides the
This register provides the status of data transfers be-
tween the UART and the host. If IER bit-2 is set to a
logic 1, an LSR interrupt will be generated immediate-
ly when any character in the RX FIFO has an error
(parity, framing, overrun, break).
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or
• Logic 1 = Data has been received and is saved in
LSR[1]: Receiver Overrun Error Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condi-
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did
LSR[4]: Receive Break Error Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX
4.8 L
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one (default).
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
FIFO (default).
the receive holding register or FIFO.
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error. If IER bit-
2 is set, an interrupt will be generated immediately.
does not have correct parity information and is sus-
pect. This error is associated with the character
available for reading in RHR.
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
was a logic 0 for at least one character frame time).
In the FIFO mode, only one break character is
loaded into the FIFO. The break indication remains
until the RX input returns to the idle condition,
“mark” or logic 1.
INE
S
TATUS
R
EGISTER
(LSR) - R
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