XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 22

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

• LSR interrupt is cleared by a read to the LSR regis-
• RXRDY interrupt is cleared by reading data until
• RXRDY Time-out interrupt is cleared by reading
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR con-
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt
at interrupt priority levels (See Interrupt Source
Table 9).
ISR[5:4]: Interrupt Status
These bits are enabled when EFR bit-4 is set to a log-
ic 1. ISR bit-4 indicates that the receiver detected a
data match of the Xoff character(s). Note that once
set to a logic 1, the ISR bit-4 will stay a logic 1 until a
Xon character is received. ISR bit-5 indicates that
CTS# or RTS# has changed state.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are
disabled. They are set to a logic 1 when the FIFOs
are enabled.
This register is used to enable the FIFOs, clear the
FIFOs, set the transmit/receive FIFO trigger levels,
4.5 FIFO C
P
4.4.2 Interrupt Clearing:
ter (but flags and tags not cleared until character(s)
that generated the interrupt(s) has been emptied or
cleared from FIFO).
FIFO falls below the trigger level.
RHR.
tents may be used as a pointer to the appropriate
interrupt service routine.
RIORITY
L
EVEL
1
2
3
4
5
6
7
-
B
IT
ONTROL
0
0
0
0
0
0
1
0
-5
B
R
IT
0
0
0
0
0
1
0
0
-4
EGISTER
ISR R
B
EGISTER
IT
3.3V AND 5V DUART WITH 128-BYTE FIFO
T
0
1
0
0
0
0
0
0
ABLE
-3
(FCR) - W
B
9: I
S
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
RITE
B
B
ITS
-O
IT
1
0
0
1
0
0
0
0
-1
NLY
S
OURCE AND
22
B
• TXRDY interrupt is cleared by a read to the ISR
• MSR interrupt is cleared by a read to the MSR reg-
• Xoff or Special character interrupt is cleared by a
• RTS# and CTS# flow control interrupts are cleared
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO
• Logic 1 = Enable the transmit and receive FIFOs.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default).
• Logic 1 = Reset the receive FIFO pointers and
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and
IT
0
0
0
0
0
0
0
1
register or writing to THR.
ister.
read to ISR.
by a read to the MSR register.
-0
(default).
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FIFO level counter logic (the receive shift register is
not cleared or altered). This bit will return to a logic
0 after resetting the FIFO.
FIFO level counter logic (the transmit shift register
is not cleared or altered). This bit will return to a
logic 0 after resetting the FIFO.
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default)
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
XR16C2850
REV. 2.0.0