XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 15

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
time taken to send two characters at the programmed
baud rate) after the receive FIFO crosses the pro-
grammed trigger level (for all trigger tables A-D). To
clear this condition, the 2850 will transmit the pro-
grammed Xon-1,2 characters as soon as receive
FIFO is less than one trigger level below the pro-
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
A special character detect feature is provided to de-
tect an 8-bit character when bit-5 is set in the En-
hanced Feature Register (EFR). When this character
(Xoff2) is detected, it will be placed in the FIFO along
with normal incoming RX data.
The 2850 compares each incoming receive character
with Xoff-2 data. If a match exists, the received data
will be transferred to FIFO and ISR bit-4 will be set to
indicate detection of special character. Although the
Internal Register Table shows Xon, Xoff Registers
with eight bits of character information, the actual
number of bits is dependent on the programmed word
length. Line Control Register (LCR) bits 0-1 defines
the number of character bits, i.e., either 5 bits, 6 bits,
7 bits, or 8 bits. The word length selected by LCR bits
0-1 also determines the number of bits that will be
used for the special character comparison. Bit-0 in
the Xon, Xoff Registers corresponds with the LSB bit
for the receive character.
The auto RS485 half-duplex direction control chang-
es the behavior of the transmitter when enabled by
FCTR bit-3. It de-asserts RTS# output following the
last stop bit of the last character that has been trans-
mitted. This helps in turning around the transceiver to
receive the remote station’s response. When the host
is ready to transmit next polling data packet again, it
characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.16 S
2.17 A
RX T
RIGGER
PECIAL
UTO
16
24
28
8
RS485 H
L
EVEL
C
HARACTER
INT P
ALF
-
T
DUPLEX
ABLE
IN
D
A
16
24
28
ETECT
8
3.3V AND 5V DUART WITH 128-BYTE FIFO
CTIVATION
6: A
C
ONTROL
UTO
X
ON
/X
X
(
OFF
CHARACTERS IN RX FIFO
OFF
C
(S
HARACTER
15
OFTWARE
16*
24*
28*
8*
grammed trigger level (for Trigger Tables A, B, and C)
or when receive FIFO is less than the trigger level mi-
nus the hysteresis value (for Trigger Table D). This
hysteresis value is the same as the Auto RTS Hyster-
esis value in Table 13. Table 6 below explains this
when Trigger Table-B (See Table 10) is selected.
only has to load data bytes to the transmit FIFO. The
transmitter automatically re-asserts RTS# output pri-
or sending the data.
The 2850 UART includes the infrared encoder and
decoder compatible to the IrDA (Infrared Data Associ-
ation) version 1.0. The IrDA 1.0 standard that stipu-
lates the infrared encoder sends out a 3/16 of a bit
wide HIGH-pulse for each “0” bit in the transmit data
stream. This signal encoding reduces the on-time of
the infrared LED, hence reduces the power consump-
tion. See Figure 12 below.
The infrared encoder and decoder are enabled by
setting MCR register bit-6 to a ‘1’. When the infrared
feature is enabled, the transmit data output, TX, idles
at logic zero level. Likewise, the RX input assumes an
idle level of logic zero from a reset and power up, see
Figure 12.
Typically, the wireless infrared decoder receives the
input pulse from the infrared sensing diode on the RX
pin. Each time it senses a light pulse, it returns a logic
1 to the data bit stream. However, this is not true with
some infrared modules on the market which indicate
a logic 0 by a light pulse. So the 2850 has a provision
to invert the input polarity to accomodate this. In this
case user can enable FCTR bit-2 to invert the input
signal.
2.18 I
(
S
) S
) F
NFRARED
ENT
LOW
)
C
ONTROL
M
ODE
X
(
CHARACTERS IN RX FIFO
ON
C
HARACTER
16
24
0
8
(
S
) S
ENT
)