XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 27

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
REV. 2.0.0
This register replaces SPR (during a Write) and is ac-
cessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Count (Write-
Only)
When Scratchpad Swap (FCTR[6]) is asserted, EM-
SR bits 1-0 controls what mode the FIFO Level
Counter is operating in.
During Alternate RX/TX FIFO Counter Mode, the first
value read after EMSR bits 1-0 have been asserted
will always be the RX FIFO Counter. The second val-
ue read will correspond with the TX FIFO Counter.
The next value will be the RX FIFO Counter again,
then the TX FIFO Counter and so on and so forth.
EMSR[3:2]: Reserved
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
4.11 E
FCTR[6]
EMSR
B
IT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
-5
T
NHANCED
ABLE
T
ABLE
EMSR[1] EMSR[0] Scratchpad is
EMSR
B
12: S
IT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
-4
13: A
M
ODE
CRATCHPAD
FCTR
B
UTO
IT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S
-1
X
ELECT
0
1
0
1
RTS H
FCTR
3.3V AND 5V DUART WITH 128-BYTE FIFO
B
S
R
Scratchpad
RX FIFO Counter Mode
TX FIFO Counter Mode
RX FIFO Counter Mode
Alternate RX/TX FIFO
Counter Mode
IT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WAP
YSTERESIS
EGISTER
-0
S
(C
ELECTION
H
HARACTERS
YSTERESIS
(EMSR)
RTS#
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
±4
±6
±8
±8
0
)
27
The FIFO Level Register replaces the Scratchpad
Register (during a Read) when FCTR[6] = 1. Note
that this is not identical to the FIFO Data Count Reg-
ister which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the
RX FIFO or the TX FIFO or both depending on EM-
SR[1:0]. See Table 12 for details.
The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value which is used to calcu-
late the baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
This register contains the device ID (0x12 for
XR16C2850). Prior to reading this register, DLL and
DLM should be set to 0x00.
This register contains the device revision information.
For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level
Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels
when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic
0) and the TX Trigger Level (a logic 1).
This register is accessible when LCR = 0xBF. Note
that this register is not identical to the FIFO Level
Register which is located in the general register set
when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters
in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7]
= 0) can be read via this register.
4.12 FIFO L
4.13 B
4.14 D
4.15 D
4.16 T
4.17 FIFO D
DLM) - R
O
O
(TRG) - W
RIGGER
AUD
EVICE
EVICE
NLY
NLY
R
EVEL
ATA
I
ATE
DENTIFICATION
R
L
EAD
EVISION
RITE
EVEL
C
R
G
/W
OUNT
EGISTER
ENERATOR
-O
RITE
/ FIFO D
NLY
R
R
EGISTER
EGISTER
(FLVL) - R
R
EGISTER
ATA
R
EGISTERS
(FC) - R
C
(DREV) - R
OUNT
(DVID) - R
EAD
-O
(DLL
EAD
R
EGISTER
NLY
-O
AND
EAD
EAD
NLY