XR16C2850CM48 EXAR [Exar Corporation], XR16C2850CM48 Datasheet - Page 43

• Manufacturer Part Number: XR16C2850CM48
• Description: 3.3V AND 5V DUART WITH 128-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

XR16C2850
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
4.0 INTERNAL Register descriptions ........................................................................................ 20
ABSOLUTE MAXIMUM RATINGS...................................................................................31
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 31
ELECTRICAL CHARACTERISTICS ................................................................................31
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................38
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................39
PACKAGE DIMENSIONS (40 PIN PDIP).........................................................................40
TABLE OF CONTENTS ................................................................................................................................. I
T
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
4.1 R
4.2 T
4.3 I
4.4 I
4.5 FIFO C
4.6 L
4.7 M
4.8 L
4.9 M
4.10 S
4.11 E
4.12 FIFO L
4.13 B
4.14 D
4.15 D
4.16 T
4.17 FIFO D
4.18 F
4.19 E
4.20 S
DC E
AC E
TA=0
R
EVISION
8: INTERNAL REGISTERS DESCRIPTION. S
9: I
10: T
11: P
12: S
13: A
14: T
15: S
16: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 30
4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 20
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation .................................................................... 20
4.4.1 Interrupt Generation: ................................................................................................................................ 21
4.4.2 Interrupt Clearing:..................................................................................................................................... 22
NTERRUPT
NTERRUPT
14. C
15. M
16. D
17. D
18. R
19. T
20. R
21. R
22. T
23. T
INE
INE
RANSMIT
LECTRICAL
ECEIVE
LECTRICAL
O TO
ODEM
ODEM
NTERRUPT
RIGGER
CRATCH
NHANCED
AUD
NHANCED
OFTWARE
EVICE
EVICE
EATURE
RANSMIT AND
RIGGER
ARITY SELECTION
CRATCHPAD
UTO
OFTWARE
C
S
RANSMIT
RANSMIT
RANSMIT
LOCK
ATA
ATA
ECEIVE
ECEIVE
ECEIVE
ODEM
H
TATUS
ONTROL
70
R
ONTROL
ISTORY
RTS H
C
S
EVEL
B
B
ATA
H
ATE
I
R
TATUS
O
ONTROL
DENTIFICATION
T
US
US
H
I
T
L
OLDING
EVISION
IMING
NPUT
S
C (-40
P
R
R
R
E
S
C
ABLE
EVEL
OLDING
F
R
R
R
OURCE AND
C
C
R
W
EADY
EADY
EADY
M
F
AD
F
NABLE
TATUS
C
ONTROL
R
G
LOW
YSTERESIS
EADY
EADY
EADY
EAD
S
R
EATURE
HARACTERISTICS
LOW
HARACTERISTICS
RITE
ODE
OUNT
....................................................................................................................................41
R
R
EGISTER
/O
WAP
ENERATOR
EGISTER
.................................................................................................................................................................... 33
R
R
S
ECEIVE
R
EGISTER
UTPUT
ELECT
C
& I
& I
& I
/ FIFO D
T
................................................................................................................................................................ 24
O TO
EGISTER
EGISTER
R
EGISTER
T
& I
& I
& I
R
ONTROL
IMING
R
S
C
S
IMING
NTERRUPT
NTERRUPT
NTERRUPT
R
R
R
EGISTER
EGISTER
ELECTION
NTERRUPT
NTERRUPT
NTERRUPT
EGISTER
R
ONTROL
ELECT
EGISTER
EGISTER
EGISTER
R
P
....................................................................................................................................................... 27
....................................................................................................................................................... 28
R
FIFO T
EGISTER
T
+85
RIORITY
EGISTER
..................................................................................................................................................... 34
IMING
(LSR) - R
.................................................................................................................................................... 34
EGISTER
(FLVL) - R
R
F
(LCR) - R
R
ATA
(FCR) - W
(SPR) - R
EGISTER
UNCTIONS
O
(MSR) - R
R
EGISTERS
............................................................................................................................................ 27
T
T
T
RIGGER
C
F
(MCR)
(RHR) - R
T
T
T
EGISTER
R
IMING
IMING
IMING
(DREV) - R
OR
L
(IER) - R
(ISR) - R
IMING
IMING
IMING
(THR) - W
............................................................................................................32
C
FOR INDUSTRIAL GRADE PACKAGE
EVEL
EGISTERS
...........................................................................................................31
(FC) - R
(FCTR) - R
OUNT
C
(EFR) ............................................................................................ 28
EAD
HANNELS
[N
[FIFO M
[FIFO M
............................................................................................................................... 22
L
............................................................................................................................... 29
[N
[FIFO M
[FIFO M
EAD
(DVID) - R
EAD
EVEL
ON
OR
EAD
ON
RITE
EAD
(DLL
(EMSR) ................................................................................. 27
-FIFO M
O
R
HADED BITS ARE ENABLED WHEN
-O
-FIFO M
EAD
EAD
/W
EAD
G
EAD
NLY
EGISTER
S
/W
(XOFF1, XOFF2, XON1, XON2) - R
ODE
ODE
RITE
-O
ELECTION
EAD
A & B......................................................................................................... 33
ENERAL
NLY
O
ODE
ODE
RITE
- O
/W
-O
RITE
AND
-O
NLY
EAD
NLY
, DMA D
, DMA E
..................................................................................... 25
ODE
, DMA M
, DMA M
-O
NLY
O
................................................................................... 27
RITE
EAD
NLY
ODE
NLY
................................................................................. 24
/W
NLY
NLY
II
DLM) - R
]
............................................................................... 22
............................................................................... 26
............................................................................... 26
.................................................................................................... 23
(TRG) - W
FOR
]
P
RITE
FOR
............................................................................ 21
............................................................................ 27
O
ISABLED
NABLED
........................................................................... 20
........................................................................... 20
URPOSE
ODE
ODE
......................................................................... 20
NLY
......................................................................... 27
C
C
HANNELS
HANNELS
.................................................................... 28
D
E
.................................................................. 27
]
]
ISABLED
NABLED
EAD
FOR
FOR
RITE
O
UTPUTS
/W
C
A & B................................................................. 35
C
A & B............................................................... 35
HANNELS
), V
]
HANNELS
-O
]
RITE
FOR
EFR B
FOR
NLY
CC IS
C
C
............................................... 27
HANNELS
C
HANNELS
IT
A & B ................................................ 36
............................................. 27
A & B ............................................... 36
ONTROL
-4=1 ................................................ 19
3.3
OR
A & B .................................... 37
A & B ................................... 37
EAD
- R
5.0V ±10% .............32
/W
EAD
RITE
/W
áç
áç
áç
áç
RITE
............... 30
........ 24