CP2400 SILABS [Silicon Laboratories], CP2400 Datasheet - Page 63

• Manufacturer Part Number: CP2400
• Description: 128/64 SEGMENT LCD DRIVER
• Manufacturer: SILABS [Silicon Laboratories]

10.3. Active Mode Port Match
Port match functionality allows system events to be triggered by a logic value change on a GPIO pin. A software
controlled value stored in the PnMATCH registers specifies the expected or normal logic values of the associated
Port. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the software
controlled value. This allows software to be notified if a certain change or pattern occurs on an input pin.
The PnMSK registers can be used to individually select which pins should be compared against the PnMATCH
registers. A Port mismatch event is generated if (PnIN & PnMSK) does not equal (PnMATCH & PnMSK) for all
Ports.
A Port mismatch event may be used to generate an interrupt. See “7. Interrupt Sources” on page 40 for more
details on handling an interrupt.
SFR Definition 10.1. PMATCHST: Port Match Status Register
Address = 0xD0
Name
Reset
Type
7:5
Bit
Bit
4
3
2
1
0
Unused
R/W
Name
P4M
P3M
P2M
P1M
P0M
7
0
Read = 000b. Write = Don’t Care.
Port 4 Match.
0: No port mismatch events have been detected on P4.
1: A port mismatch event is present on P4.
Port 3 Match.
0: No port mismatch events have been detected on P3.
1: A port mismatch event is present on P3.
Port 2 Match.
0: No port mismatch events have been detected on P2.
1: A port mismatch event is present on P2.
Port 1 Match.
0: No port mismatch events have been detected on P1.
1: A port mismatch event is present on P1.
Port 0 Match.
0: No port mismatch events have been detected on P0.
1: A port mismatch event is present on P0.
R/W
6
0
R/W
5
0
Rev. 1.0
P4M
R/W
4
0
Function
P3M
R/W
3
0
P2M
R/W
2
0
CP2400/1/2/3
P1M
R/W
1
0
P0M
R/W
0
0
63