CP2400 SILABS [Silicon Laboratories], CP2400 Datasheet - Page 102

• Manufacturer Part Number: CP2400
• Description: 128/64 SEGMENT LCD DRIVER
• Manufacturer: SILABS [Silicon Laboratories]

CP2400/1/2/3
14.2. Serial Clock Timing
The clock to data relationship is shown in Figure 14.2. If the SPI master is a C8051 microcontroller, its SPI
peripheral must be configured for Mode 0 communication (CKPOL = 0, CKPHA = 0).
The maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided
that the master issues SCK, NSS, and the serial input data synchronously with the system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less
than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the
device and does not need to receive data back (i.e. half-duplex operation), the slave can receive data at a
maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues
SCK, NSS, and the serial input data synchronously with the system clock.
102
SCK
(CKPOL=0, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)
MSB
MSB
Bit 6
Bit 6
Figure 14.2. Data/Clock Timing
Bit 5
Bit 5
Rev. 1.0
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0