CP2400 SILABS [Silicon Laboratories], CP2400 Datasheet - Page 51

• Manufacturer Part Number: CP2400
• Description: 128/64 SEGMENT LCD DRIVER
• Manufacturer: SILABS [Silicon Laboratories]

9.3.
In Ultra Low Power LCD Mode, the on-chip LDO is placed in a low power state and power is gated off from all
digital logic residing outside the ULP block. The ULP block allows the device to refresh an LCD, maintain a real
time clock, detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events. The Port Match
functionality in ULP Mode differs from the functionality of Port Match when the device is in Normal or RAM
Preservation Mode. See Section “9.7. Port Match Functionality in the Ultra Low Power Modes” on page 56 for more
details.
All Port I/O with the exception of P3.3-P4.3 must be configured to Analog mode prior to entering ULP Mode.
From Normal Mode, the device can be placed in ULP LCD Mode using the following procedure:
The device will not enter ULP mode if there are pending wake-up events, and the INT pin will remain asserted. To
ensure that the device has successfully entered the low power mode, the host processor should verify that there
are no pending wake-up events prior to placing the device in a ULP mode and that the INT pin remains de-asserted
for 100 µs after placing the device in ULP mode. If the INT pin is found to be asserted, then the host controller
should treat the situation as if the device has entered ULP and has been awoken by a wake-up event. The state of
RAM and unpreserved registers should not be relied upon since the host controller will not be able to determine if
the regulator has been disabled and re-enabled, or never disabled. The Port Match, SmaRTClock Alarm, and
SmaRTClock Oscillator Fail interrupts should always be enabled any time the device is placed in a ULP mode.
Once the device enters ULP LCD Mode, it will remain in this low power mode until a SmaRTClock Alarm,
SmaRTClock Oscillator Fail, or ULP Port Match wake-up event occurs. Once the device wakes up, it will generate
a reset complete interrupt and assert the INT pin. The host controller may also wake up the device at any time.
To resume Normal Mode operation, the host controller should use the following procedure:
Note: The Port I/O state and configuration settings are preserved as long as the device is in the low power mode. Upon wake-
In the ULP LCD Mode, the SmaRTClock oscillator may be disabled if a low frequency CMOS clock (~32 kHz) is
present at CLK pin. Set the RTCBYP bit (MSCN.7) to logic 1 in order to override the SmaRTClock with the CMOS
clock available at the CLK pin. The SmaRTClock should be disabled by writing 0x00 to the indirect RTC0CN
register instead of setting the RTCDIS bit (ULPCN.4) while entering ULP LCD Mode. When the SmaRTClock is
disabled, SmaRTClock alarm and SmaRTClock oscillator fail detection functionality is no longer available.
up, all Port I/O state and configuration settings will reset, making all Port I/O digital inputs with weak pullups enabled.
They will remain in this state until the host controller re-initializes the Port I/O state and configuration registers.
Ultra Low Power LCD Mode
1. Set INT0EN:INT1EN to 0x1900. This enables the SmaRTClock Fail, SmaRTClock Alarm, and Port
2. Configure the bandgap into one of its low power modes by writing 0xC0 or 0x80 to MSCF. Choosing
3. Drive the PWR or NSS pin LOW.
4. Set the LCDEN (ULPCN.3) to logic 1. If Port Match functionality is desired, also set the ULPEN
5. Drive the PWR or NSS pin HIGH.
1. Drive the PWR or NSS pin LOW.
2. Wait for the INT pin to be asserted. See Table 3.4 for ULP Mode wake up time.
3. Re-initialize all registers which are not preserved during ULP mode. See Table 6.3 for a list of registers
Match interrupts and disables all others.
the loose bandgap regulation (MSCF = 0x80) will result in the lowest supply current at the expense of
increased ripple in the LCD output voltage.
(ULPCN.1) bit to logic 1.
that preserve their state in ULP mode.
Rev. 1.0
CP2400/1/2/3
51