SI2107 SILABS [Silicon Laboratories], SI2107 Datasheet
SI2107
Related parts for SI2107
SI2107 Summary of contents
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... Digital video recorders Digital televisions Description The Si2107/08/09/10 are a family of pin-compatible, complete front-end solutions for DSS and DVB-S digital satellite reception. The IC family incorporates a tuner, demodulator, and LNB controller into a single device resulting in significantly reduced board space and external component count. The device supports symbol rates MBaud over a 950 to 2150 MHz range ...
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... Si2107/08/09/10 2 Preliminary Rev. 0.7 ...
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... Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6. Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.7. LNB Signaling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8. On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only I2C Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10. Ordering Guide1 11. Package Outline: 44-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Si2107/08/09/10 Preliminary Rev. 0.7 Page 3 ...
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... Permanent damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operations sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The Si2107/08/09/ high-performance RF integrated circuit. Handling and assembly of these devices should only be done at ESD-protected workstations. 4 ...
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... Min gain L 950 to 2150 MHz LO 100 kHz offset MHz offset N 10 kHz to 1/2 Baud LO Rate At 20 MHz offset At 2 kHz offset t s, Preliminary Rev. 0.7 Si2107/08/09/10 Min Typ Max Unit — 313 — mA — 298 — mA — 292 — mA — 217 — ...
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... Si2107/08/09/10 Table 5. Receiver Characteristics Parameter RF input frequency range Fine tune step size Symbol rate range Carrier offset correction range Table 6. LNB Supply Characteristics (Si2108/10 Only) Parameter Supply Voltage Converter Switch Frequency Output HIGH voltage Output LOW voltage Low to High Transition Time ...
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... SU, DAT t HD, DAT SU, STA t SU,STO SU;DAT HIGH SU;STA r 2 Figure Timing Diagram Preliminary Rev. 0.7 Si2107/08/09/10 Min Typ Max 0 — 400 1.3 — — 0.6 — — 1.3 — — 0.6 — — 100 — — 0 — 0.9 — — ...
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... Si2107/08/09/10 Table 8. MPEG-TS Specifications (Rising Launch and Capture) Parameter Symbol Clock cycle time t cycle Clock low time t clow Clock high time t chigh Hold time t hold Setup time t setup Access time t access L TS_CLK TS_DATA t hold Figure 2. MPEG-TS (Rising Launch and Capture) Timing Diagram ...
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... Serial mode (TSSCR = 01) Serial mode (TSSCR = 11) Parallel mode Normal operation Data delayed (TSDD = 1) Clock Delayed (TSCD = 1) Normal operation Data delayed (TSDD = 1) Clock Delayed (TSCD = 1) t cycle C t hold t setup t access Preliminary Rev. 0.7 Si2107/08/09/10 Min Typ Max Unit 11.3 — 28 — 8000 ns 5.1 — 6.9 ns 12.0 — ...
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... Si2107/08/09/10 2. Typical Application Schematic 10 2 VDD_LNA XTAL1 1 35 REXT XTAL2 2 34 ADDR VDD_XTAL 3 33 VDD_MIX XTOUT 4 32 VDD_BB VDD_PLL33 5 31 VDD_ADC INT/RLK/GPO 6 30 TDET/VSEN TS_ERR 7 29 TGEN/LNB1 TS_VAL 8 28 NC/ISEN TS_SYNC 9 27 DRC/LNB2 SDA 10 26 RESET SCL 11 25 DCS/PWM TS_DATA7 12 24 ...
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... Si2110 LNB Control Si2110 LNB Control Preliminary Rev. 0.7 Si2107/08/09/10 11 ...
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... Si2107/08/09/10 12 Si2110 LNB Control Si2110 LNB Control Preliminary Rev. 0.7 ...
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... Bill of Materials Table 10. Si2107/08/09/10 Bill of Materials Component C1,C2,C4,C6,C10,C8,C9, C10,C13,C14,C15,C16 C5 C3,C7,C11,C12 C19,C36 TC1 Notes: 1. Tuning component values depend on the balun selected and layout. Contact Silicon Laboratories for assistance reviewing layouts and selecting matching components. 2. The transient voltage suppression device should be selected to match the surge requirements of the application ...
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... Si2107/08/09/10 Table 11. DiSEqC 1.x LNB Supply Bill of Materials (Si2108/10 Only) Component C30 47 µF, 25 V,Electrolytic,± 20% C31 0.47 µ X7R,± 20% C32 C33 0.22 µ X7R, ± 20% C34 D1 ZHCS750TA 750 mA D3 MMBD1705, Dual diode DR78098,33 µH,1 Q3,Q5, ...
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... R13 R14 43 kΩ, 62.5 mW, ±5% R15 3 kΩ, 100 mW, ±5% R16 2 kΩ, 250 mW, ±5% R17 2.2 kΩ, 62.5 mW, ±1% 16 Ω, 250 mW, ±5% R18 Si2107/08/09/10 Central Semiconductor Preliminary Rev. 0.7 Vendor Zetex Fairchild Datatronic ACT Datatronic ACT Zetex Fairchild Zetex ...
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... LNB supply regulator circuit. The LNB supply controller utilizes a step-up converter architecture. In case operation with an external regulator is desired, Si2107 and Si2109 can be used; these do not integrate the LNB step-up dc-dc controller. On the other hand, the Si2109 and Si2110 integrate an on-chip “ ...
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... Functional Description The Si2107/08/09/ family of highly-integrated CMOS RF satellite receivers for DVB-S and DSS applications. The device is an ideal solution for satellite set-top boxes, digital video recorders, digital televisions, and satellite PC-TV. The IC incorporates a tuner, demodulator, and LNB controller into a single device resulting in a significant reduction in board space and external component count ...
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... For each valid DVB-S/DSS channel, the tuning frequency and symbol rate, which can be stored by the host for subsequent tuning, are determined. On Si2107/ 08 devices, the host needs to provide the channel tuning frequency and symbol rate to the device. ...
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... The TS_ERR output is active during the entire erred TS frame. The polarity of TS_ERR can be programmed to be active high or active low using the TSEP bit. Si2107/08/09/10 All signals on the MPEG-TS output interface can be individually tri-stated using bits TSE_OE, TSV_OE, TSS_OE, TSC_OE, and TSD_OE. ...
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... Si2107/08/09/10 Parallel Data Mode TS_CLK, rising edge TS_DATA[7:0] TS1 (sync) TS_SYNC active high TS_VAL active high TS_ERR active high Continuous Serial Data Mode TS_CLK rising edge TS1 (sync) TS_DATA[0] TS_SYNC, active low/1-bit wide TS_VAL active low TS_ERR, active low Gapped Serial Data Mode ...
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... Message parity error Message receive timeout Short-circuit detect Overcurrent detect Si2107/08/09/10 Interrupt bits are set by the device to 1 when an interrupt occurs. The host clears an interrupt bit by writing a 1 again, at which time the device resets the interrupt bit to zero. Table 16 illustrates the interrupt sources and their associated status, enable, and interrupt bits ...
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... Viterbi code rate search (VTF), frame sync search (FSF), and overall receiver acquisition (AQF), 6.4. Tuning Control The Si2107/08/09/10 utilizes a unique two-stage tuning algorithm to provide optimal RF reception. The input signal is first mixed down to a low-IF frequency by a coarse tuning stage and then down to baseband by a fine-tune mixer ...
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... If symbol rate estimation is not required, the user should program the symbol rate explicitly into the SR register. This is the only mode of operation for Si2107/08. On Si2109/10, the symbol rate unknown bit, SRUK, can be changed from its default value to activate symbol rate estimation ...
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... Si2107/08/09/10 6.4.7. C/N Estimator A carrier-to-noise estimator is provided to aid in satellite antenna positioning. The C/N measurement mode bit, CNM, controls whether the count is performed over a fixed-length or infinite window. With a fixed-length window, the window size is defined by register CNW. Measurements are stored in a 16-bit saturating register, CNL. Setting the C/N estimator start bit, CNS clears the CNL register and initiates the C/N measurement ...
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... If an inversion is detected, data are inverted prior to being output. 6.6. Automatic Gain Control The Si2107/08/09/10 is equipped with the ability to adjust signal levels via an automatic gain control (AGC) loop. This ensures that the noise and linearity characteristics of the signal path are optimized at all times ...
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... Si2107/08/09/10 6.6.2. Digital AGC Downstream of the analog VGAs, after A/D conversion of the signal, there are two points at which the digital gain can be programmed. Digital AGC1 is used to change signal power after removal of adjacent channels by the (digital) anti-aliasing filter. By default, DAGC1 is enabled and periodically adjusts the gain of the I & ...
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... MSGRL register. 6.7.4. LNB Signaling Modes 6.7.4.1. Automatic LNB Messaging Mode 1.0 ms The Si2107/08/09/10 LNB Signaling Controller can fully manage the generation and sequencing of all LNB commands. The device is configured in this mode by appropriately programming the LNB Messaging mode register, LNBM. To initiate a message sequence, the ...
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... Si2107/08/09/10 When the sequence has completed, the device clears the LNB sequence start bit, LNBS, automatically. Note that, when operating in this mode, the DRC pin is high while transmitting and low while receiving. End of continuous Change of voltage tone (if present) (if required) 1st message (no reply requested) > ...
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... In the event that the LNB supply circuit is accidentally connected to a voltage source greater than the intended output voltage, it remains operational. The LNB supply circuit resumes normal operation when the connection to the external voltage source has been removed. Preliminary Rev. 0.7 Si2107/08/09/10 29 ...
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... Si2107/08/09/10 7. I2C Control Interface The I2C bus interface is provided for configuration and monitoring of all internal registers. The Si2107/08/09/10 supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. Individual data transfers to and from the device are 8-bits. The I2C bus consists of two wires: a serial clock line (SCL) and a serial data line (SDA) ...
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... CEL_I SRL_I STL_I STU_I CRU_I VTU_I RSER_I MSGPE_I FE_I Receiver Status CEL SRL STL CEF SRF STF Tuning Control ADCSR[7:0] CTF[7:0] Preliminary Rev. 0.7 Si2107/08/09/ REV[3:0] SYSM[2:0] TSCE TSDF TSM TSPG TSSCR[1:0] TSS_OE TSC_OE TSD_OE GPO PSEL[1:0] CRL_E VTL_E FSL_E FSU_E ...
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... Si2107/08/09/10 Name I2C D7 Addr. Fine Tune L 17h Fine Tune H 18h CE Ctrl 29h CE Offset L 36h CE Offset H 37h CE Err L 38h CE Err H 39h SR Ctrl 3Ah SRUK Sym Rate L 3Fh Sym Rate M 40h Sym Rate H 41h SR Max 42h SR Min 43h CN Ctrl 7Ch CNS CN TH 7Dh ...
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... DAGC2GA[7:0] DAGC2GA[15:8] LNB Supply Controller LNBCT LNBB MMSG TT TR TFQ[7:0] FF MSGPE MSGR MSGTO FIFO1[7:0] FIFO2[7:0] FIFO3[7:0] FIFO4[7:0] FIFO5[7:0] FIFO6[7:0] VLOW[3:0] IMAX[1:0] VMON[7:0] Preliminary Rev. 0.7 Si2107/08/09/ AGCO[3:0] AGC1[3:0] AGC3[3:0] DAGC2W[1:0] DAGC2TDIS MSGL[2:0] BRST_DS TFS MSGRL[2:0] VHIGH[3:0] SLOT[1:0] OLOT[1: ...
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... Si2107/08/09/10 Table 19. Register Summary (Continued) Name I2C D7 D6 Addr. LNB S Ctrl4 CEh LNBL LNB S Stat CFh LNB_EN COMP Preliminary Rev. 0 LNBLVL LNBMD I SCD OCD S ...
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... Bit Name 7:6 Reserved 5 INC_DS 4:3 MOD[1:0] 2:0 SYSM[2: Function Device ID Si2110 1h = Si2109 2h = Si2108 3h = Si2107 Revision. Current revision = INC_DS MOD[1:0] Function Program to zero. I2C Automatic Address Increment Disable Enabled (default Disabled Modulation Selection BPSK Demodulation 01 = QPSK Demodulation (default Reserved 11 = Reserved System Mode ...
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... Si2107/08/09/10 Register 02h. Transport Stream Control 1 Bit D7 D6 Name TSEP TSVP Bit Name 7 TSEP 6 TSVP 5 TSSP 4 TSSL 3 TSCM 2 TSCE 1 TSDF 0 TSM TSSP TSSL TSCM Transport Stream Error Polarity Active high (default Active low Transport Stream Valid Polarity Active high (default Active low Transport Stream Sync Polarity ...
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... Normal operation (default Delay data relative to clock Transport Stream Parity Gate Normal operation (default Zero data lines during parity Transport Stream Serial Clock Rate 80–88.5 MHz (default 76.8–82.8 MHz 10 = 54.9–59.2 MHz 11 = 35–37.7 MHz Preliminary Rev. 0.7 Si2107/08/09/ TSPG TSSCR[1:0] Function 37 ...
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... Si2107/08/09/10 Register 04h. Pin Control 1 Bit D7 D6 Name INT_EN INTT Bit Name 7 INT_EN 6 INTT 5 INTP 4 TSE_OE 3 TSV_OE 2 TSS_OE 1 TSC_OE 0 TSD_OE INTP TSE_OE TSV_OE Interrupt Pin Enable Disabled (default Enabled Interrupt Pin Type CMOS (default Open drain/source Interrupt Polarity Active low (default Active high Transport Stream Error Output Enable ...
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... Program to zero. Descrambler Bypass Normal operation (default Bypass Note: This bit is ignored in DSS mode; the descrambler is automatically bypassed. Reed-Solomon Bypass Normal operation (default Bypass Deinterleaver Bypass Normal operation (default Bypass Program to zero. Preliminary Rev. 0.7 Si2107/08/09/ GPO PSEL[1:0] Function ...
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... Si2107/08/09/10 Register 07h. Interrupt Enable 1 Bit D7 D6 Name RCVL_E AGCL_E Bit Name 7 RCVL_E 6 AGCL_E 5 CEL_E 4 SRL_E 3 STL_E 2 CRL_E 1 VTL_E 0 FSL_E CEL_E SRL_E STL_E Function Receiver Lock Interrupt Enable Disabled (default Enabled AGC Lock Interrupt Enable Disabled (default Enabled Carrier Estimator Lock Interrupt Enable. ...
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... Disabled (default Enabled Carrier Recovery Unlock Interrupt Enable Disabled (default Enabled Viterbi Search Unlock Interrupt Enable Disabled (default Enabled Frame Sync Unlock Interrupt Enable Disabled (default Enabled Program to zero. Acquisition Fail Interrupt Enable Disabled (default Enabled Preliminary Rev. 0.7 Si2107/08/09/ FSU_E 0 AQF_E 41 ...
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... Si2107/08/09/10 Register 09h. Interrupt Enable 3 Bit D7 D6 Name CN_E VTBER_E RSER_E Bit Name 7 CN_E 6 VTBER_E 5 RSER_E 4 MSGPE_E 3 FE_E 2 FF_E 1 MSGR_E 0 MSGTD_E MSGPE_E FE_E C/N Estimator Interrupt Enable Disabled (default Enabled Viterbi BER Interrupt Enable Disabled (default Enabled Reed-Solomon Error Measurement Interrupt Enable. ...
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... Register 0Ah. Interrupt Enable 4 Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 SCD_E 0 OCD_E Function Program to zero. Short Circuit Detect Interrupt Enable Disabled (default Enabled Over Current Detect Interrupt Enable Disabled (default Enabled Preliminary Rev. 0.7 Si2107/08/09/ SCD_E OCD_E 43 ...
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... Si2107/08/09/10 Register 0Bh. Interrupt Status 1 Bit D7 D6 Name RCVL_I AGCL_I Bit Name 7 RCVL_I 6 AGCL_I 5 CEL_I 4 SRL_I 3 STL_I 2 CRL_I 1 VTL_I 0 FSL_I CEL_I SRL_I STL_I Function Receiver Lock Interrupt Disabled (default Enabled AGC Lock Interrupt Disabled (default Enabled Carrier Estimator Lock Interrupt. ...
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... Carrier Recovery Unlock Interrupt Normal operation (default Event recorded Viterbi Search Unlock Interrupt Normal operation (default Event recorded Frame Sync Unlock Interrupt Normal operation (default Event recorded Program to zero. Acquisition Fail Interrupt Normal operation (default Event recorded Preliminary Rev. 0.7 Si2107/08/09/ FSU_I 0 AQF_I 45 ...
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... Si2107/08/09/10 Register 0Dh. Interrupt Status 3 Bit D7 D6 Name CN_I VTBR_I Bit Name 7 CN_I 6 VTBR_I 5 RSER_I 4 MSGPE_I 3 FE_I 2 FF_I 1 MSGR_I 0 MSGTO_I RSER_I MSGPE_I FE_I C/N Estimator Interrupt Normal operation (default Event recorded Viterbi BER Interrupt Normal operation (default Event recorded Reed-Solomon Error Measurement Complete Interrupt. ...
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... Register 0Eh. Interrupt Status 4 Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 SCD_I 0 OCD_I Function Program to zero. Short Circuit Detect Interrupt Normal operation (default Event recorded Over Current Detect Interrupt Normal operation (default Event recorded Preliminary Rev. 0.7 Si2107/08/09/ SCD_I OCD_I 47 ...
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... Si2107/08/09/10 Register 0Fh. Lock Status 1 Bit AGCL Name Bit Name 7 Reserved 6 AGCL 5 CEL 4 SRL 3 STL 2 CRL 1 VTL 0 FSL Register 10h. Lock Status 2 Bit D7 D6 Name RCVL 0 Bit Name 7 RCVL 6:0 Reserved CEL SRL STL Function Program to zero. AGC Lock Status. ...
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... Symbol Timing Search Status Normal operation (default Search failed Carrier Search Status Normal operation (default Search failed Viterbi Search Status Normal operation (default Search failed Frame Sync Search Status Normal operation (default Search failed Preliminary Rev. 0.7 Si2107/08/09/ CRF VTF FSF 49 ...
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... Si2107/08/09/10 Register 14h. Acquisition Control 1 Bit D7 D6 Name AQS 0 Bit Name 7 AQS 6:0 Reserved Register 15h. ADC Sampling Rate Bit D7 D6 Name Bit Name 7:0 ADCSR[7:0] Register 16h. Coarse Tune Frequency Bit D7 D6 Name Bit Name 7:0 CTF[7: Function Automatic Acquisition Start. ...
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... See Register 17h AGCW[1:0] Program to zero. AGC Measurement Window. Acquisition Tracking 00 = 1024 (default) 65536 samples (default 2048 131072 samples 10 = 4096 262144 samples 11 = 8192 524288 samples Program to zero. Preliminary Rev. 0.7 Si2107/08/09/ Function f s × ------- - f = FTF fine Function D3 D2 ...
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... Si2107/08/09/10 Register 24h. AGC Control 2 Bit D7 D6 Name AGCTR[3:0] Bit Name 7:4 AGCTR[3:0] 3:0 AGCO[3:0] Register 25h. Analog AGC 1–2 Gain Bit D7 D6 Name AGC2[3:0] Bit Name 7:4 AGC2[3:0] 3:0 AGC1[3:0] Register 26h. Analog AGC 3–4 Gain Bit D7 D6 Name AGC4[3:0] Bit Name 7:4 AGC4[3:0] 3:0 AGC3[3:0] ...
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... Default: 20h AGCPWR[6:0] Function Program to zero. AGC Power Level. Represents the measured input power level after the ADC in rms format. The measurement window is set by AGCW (23h[6:4]). This register sat- urates at full scale. Default: 00h. Preliminary Rev. 0.7 Si2107/08/09/ ...
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... Si2107/08/09/10 Register 29h. Carrier Estimation Control Bit D7 D6 Name 0 0 Bit Name 7:4 Reserved 3 Reserved 2:0 CESR[2:0] Register 36h. Carrier Estimator Offset L Bit D7 D6 Name Bit Name 7:0 CFO[7: Function Program to zero. Program to one. Carrier Estimation Search Range. 000 = Reserved 001 = ± (± ...
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... Stores the carrier frequency offset that is identified during the carrier offset estimation stage. Offset = – CFER Note: CFER is a 16-bit Twos complement number. Default: 00h CFER[15:8] Function Carrier Frequency Offset Error (High Byte). See register 38h. Preliminary Rev. 0.7 Si2107/08/09/ × ------- - ...
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... Si2107/08/09/10 Register 3Ah. Symbol Rate Control (Si2109 and Si2110 only) Bit D7 D6 Name 0 SRUK Bit Name 7 Reserved 6 SRUK 5:0 Reserved Register 3Fh. Symbol Rate L Bit D7 D6 Name Bit Name 7:0 SR[7:0] Register 40h. Symbol Rate M Bit D7 D6 Name Bit Name 7:0 SR[15: Function Program to zero ...
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... Symbol Rate (High Byte). See register 3F SRMX[7:0] Function Symbol Rate Estimation Maximum. Max symbol rate Default: 00h SRMN[7:0] Function Symbol Rate Estimation Minimum. Min symbol rate Default: 00h. Preliminary Rev. 0.7 Si2107/08/09/ × ------- - = SRMX ...
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... Si2107/08/09/10 Register 75h. Digital AGC 1 Control Bit D7 D6 Name 0 DAGC1_EN Bit Name 7 Reserved 6 DAGC1_EN 5:4 DAGC1W[1:0] 3 DAGC1T 2 DAGC1HOLD 1 DAGC1HOST 0 Reserved Register 76h. Digital AGC 1 Gain L Bit D7 D6 Name Bit Name 7:0 DAGC1[7: DAGC1W[1:0] DAGC1T DAGC1HOLD Program to 0 (device may change the value of this bit during opera- ...
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... Digital AGC2 Automatic Tracking Disable 1 = Disable automatic tracking. Freeze applied to gain Enable automatic tracking. (default DAGC2T[7:0] Function Digital AGC2 Threshold Default: B5h Preliminary Rev. 0.7 Si2107/08/09/ DAGC2W[1:0] DAGC2TDIS Tracking 1024 samples (default) 2048 samples 4096 samples ...
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... Si2107/08/09/10 Register 7Ah. Digital AGC 2 Level L Bit D7 D6 Name Bit Name 7:0 DAGC2GA[7:0] Register 7Bh. Digital AGC 2 Level H Bit D7 D6 Name Bit Name 7:0 DAGC2GA[15:8] Register 7Ch. C/N Estimator Control Bit D7 D6 Name CNS 0 Bit Name 7 CNS 6:3 Reserved 2 CNM 1:0 CNW[1: DAGC2GA[7:0] Function Digital AGC2 Gain Auto (low byte) ...
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... CNL[7:0] Function C/N Estimator Level (Low Byte). The value in this register used with an external lookup table to estimate the C/N of the input signal. Default: 00h CNL[15:8] Function C/N Estimator Level (High Byte). See Register 7Eh. Preliminary Rev. 0.7 Si2107/08/09/ ...
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... Si2107/08/09/10 Register A0h. Viterbi Search Control 1 Bit D7 D6 Name 0 0 Bit Name 7:6 Reserved 5:0 VTCS[5:0] Register A2h. Viterbi Search Control 2 Bit Name Reserved Bit Name 3 VTERS 2 VTERM 1:0 VTERW[1: VTCS[5:0] Function Program to zero. Viterbi Code Rate Search Parameter Enable. The code rates to be used in the Viterbi search are selected by writing a one into the appropriate bit position ...
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... Swapped VTBRC[7:0] Function Viterbi BER Counter (Low Byte). Stores the number of the Viterbi bit errors detected within the specified measurement window. This register saturates when it reaches the limit of its range. Default: 00h Preliminary Rev. 0.7 Si2107/08/09/ VTPS VTIQS ...
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... Si2107/08/09/10 Register ACh. Viterbi BER Count H Bit D7 D6 Name Bit Name 7:0 VTBRC[15:8] Register B0h. Reed-Solomon BER Error Monitor Control Bit D7 D6 Name Reserved Bit Name 7:5 Reserved 4 RSERS 3 RSERM 2 RSERW 1:0 RSERT[1: VTBRC[15:8] Function Viterbi BER Counter (High Byte). See Register ABh. ...
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... D4 D3 RSERC[15:8] Reed-Solomon Error Counter (High Byte). See Register B1h Program to zero. Descrambler Transport Error Insertion Disable Enabled (default Disabled Descrambler Inverted SYNC Overwrite Disable Enabled (default Disabled Preliminary Rev. 0.7 Si2107/08/09/ Function Function D1 D0 DST_DS DSO_DS Function 65 ...
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... Si2107/08/09/10 Register B5h. PRBS Control Bit D7 D6 Name PRBS_START PRBS_INVERT PRBS_SYNC Bit Name 7 PRBS_START 6 PRBS_INVERT 5 PRBS_SYNC 4:2 Reserved 1:0 PRBS_HEADER_SIZE Function Start PRBS synchronization Start PRBS synchronization Default = 0 Invert PRBS output PRBS inverted. Default = 0 Synchronization achieved for PRBS test Not synchronized. ...
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... Five bytes 110 = Six bytes 111 = Longer than six bytes. Notes: 1. When message length is set to one byte, tone burst modulation is used. When message length is set to two or more bytes, DiSEqC modulation is used. 2. Not available in manual LNB mode. Preliminary Rev. 0.7 Si2107/08/09/ MSGL[2:0] 67 ...
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... Si2107/08/09/10 Register C1h. LNB Control 2 Bit D7 D6 Name LNBM[1:0] Bit Name 7:6 LNBM[1:0] 5:3 Reserved 2 BRST_DS 1 TFS 0 Reserved Register C2h. LNB Control 3 Bit D7 D6 Name TDIR TT Bit Name 7 TDIR 4:0 Reserved Function LNB Signaling Mode Automatic (default Step-by-step ...
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... D4 D3 TFQ[7:0] Function LNB Tone Frequency Control. Used to set the frequency of the LNB tone according to the following equation: Frequency = 100 MHz/[32 x (TFQ+1)] 00000000–01111011 = Reserved 01111100–10011011 = valid range 10011100–11111111 = Reserved Default: 8Dh = 22 kHz Preliminary Rev. 0.7 Si2107/08/09/ ...
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... Si2107/08/09/10 Register C4h. LNB Status Bit Name Bit Name MSGPE 4 MSGR 3 MSGTO 2:0 MSGRL[2:0] Register C5-CAh. Message FIFO 1–6 Bit D7 D6 Name Bit Name 7:0 FIFO1–6[7: MSGPE MSGR MSGTO Function Message FIFO Empty Normal operation (default) ...
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... Default: 8h resulting in low voltage = Vlow_nom + 0 Vboost. LNB Supply High Voltage High voltage = Vhigh_nom + VHIGH[3:0] x 0.0625V + Vboost, where Vhigh_nom is determined by the LNBLVL(CEh[1]) register bit, and Vboost is determined by the COMP(CEh[2]) register bit. Default: 8h resulting in High voltage = Vhigh_nom + 0 Vboost. Preliminary Rev. 0.7 Si2107/08/09/ VHIGH[3:0] 71 ...
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... Si2107/08/09/10 Register CCh. LNB Supply Control 2 (Si2108 and Si2110 only) Bit D7 D6 Name ILIM[1:0] Bit Name 7:6 ILIM[1:0] 5:4 IMAX[1:0] 3:2 SLOT[1:0] 1:0 OLOT[1:0] Note: Register CCh is lockable via LNBL (CEh[7]). When locked, this register is read-only. Register CDh. LNB Supply Control 3 (Si2110 only) Bit D7 D6 ...
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... Note: The resulting nominal output voltages are: 12/15 V (Japan) and 13/18 V (R.O.W.) when using the default settings for the VLOW (CBh[7:4]) and VHIGH (CBh[3:0]) register bits. LNB Mode Detect. Detected supply mode (read-only External LNB supply circuit 1 = Internal LNB supply circuit Preliminary Rev. 0.7 Si2107/08/09/ COMP LNBLVL LNBMD Function ...
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... Si2107/08/09/10 Register CFh. LNB Supply Status (Si2108 and Si2110 only) Bit D7 D6 Name 0 0 Bit Name 7:2 Reserved 1 SCD 0 OCD Function Program to zero. Short-Circuit Detect Flag Normal operation (default Short-circuit detected Overcurrent Detect Flag Normal operation (default Overcurrent detected. ...
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... TGEN—Outputs tone or tone envelope. Current Sense (Si2108/10 only). 9 ISEN I Monitors current of LNB supply circuit. When LNB supply circuit is not populated or when using Si2107/09, leave pin unconnected. LNB Control 2/Direction Control. LNB2 (Si2108/10 only)—required connection to LNB supply circuit. 10 LNB2/DRC I/O DRC—Outputs signal to indicate message transmission (HIGH) or reception (LOW) ...
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... Si2107/08/09/10 PWM/DC Voltage Select. PWM (Si2108/10 only)—Connected to gate of power MOSFET for LNB supply cir- 12 PWM/DCS O cuit. DCS—Outputs signal to indicate 18 V (HIGH (LOW) LNB supply voltage selection. Supply voltage. 13 VDD_DIG18 I Digital power supply. Connect to 1.8 V. Transport Stream Data Bus. ...
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... Si2107-X-FM Satellite receiver for DVB-S/DSS, Lead-free and RoHS Compliant Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. Si2107/08/09/10 Description Preliminary Rev. 0.7 Temperature ° ° ° ...
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... Si2107/08/09/10 11. Package Outline: 44-pin QFN Figure 18 illustrates the package details for the Si2110. Table 20 lists the values for the dimensions shown in the illustration. Table 20. Package Diagram Dimensions Millimeters Dimension Min Nom A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC. D2 2.70 2.80 e 0.50 BSC. E 8.00 BSC. Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. ...
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... Updated pin numbering and pin descriptions. Schematics updated. I2C interface description added. MPEG-TS timing specifications added. Revision 0.5 to revision 0.6 Data sheet for Si2107/08/09/10. Added detailed operational description. Register map changed for Rev. C silicon. Various editorial changes and corrections. Revision 0.6 to revision 0.7 Updated application diagram and BOM. ...
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... Si2107/08/09/ ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: DBSinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...