CY14B101K-SP25XCT CYPRESS [Cypress Semiconductor], CY14B101K-SP25XCT Datasheet - Page 4

• Manufacturer Part Number: CY14B101K-SP25XCT
• Description: 1 Mbit (128K x 8) nvSRAM With Real Time Clock
• Manufacturer: CYPRESS [Cypress Semiconductor]

Hardware RECALL (Power Up)
During
(V
V
RECALL cycle automatically initiates and takes t
complete.
Software STORE
Using a software address sequence, transfer the data from the
SRAM to the nonvolatile memory. The CY14B101K software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. Once a STORE cycle is initiated, further input and
output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If there are intervening
READ OR WRITE accesses, the sequence is aborted and no
STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence are performed:
The software sequence is clocked with CE controlled READs or
OE controlled READs. Once the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that READ cycles and not WRITE cycles
are used in the sequence. It is not necessary that OE is LOW for
the sequence to be valid. After the t
the SRAM is activated again for READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations are
performed:
.
Document Number: 001-06401 Rev. *G
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE cycle
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
CC
CC
< V
once again exceeds the sense voltage of V
SWITCH
power
), an internal RECALL request is latched. When
up
or
after
any
STORE
low
cycle time is fulfilled,
power
HRECALL
SWITCH
condition
, a
to
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements.
Preventing AutoStore
Disable the AutoStore function by initiating an AutoStore Disable
sequence. A sequence of READ operations is performed in a
manner similar to the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence of CE
controlled READ operations are performed:
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore Enable sequence, the following sequence of CE
controlled READ operations are performed:
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) is issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B101K protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when V
mode (both CE and WE LOW) at power up, after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brownout conditions.
Noise Considerations
The CY14B101K is a high speed memory and so must have a
high frequency bypass capacitor of approximately 0.1 µF
connected between V
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduce circuit
noise.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8B45 AutoStore Disable
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4B46 AutoStore Enable
CC
is less than V
CC
SWITCH
and V
RECALL
. If the CY14B101K is in a WRITE
SS
cycle time, the SRAM is once
, using leads and traces that
CY14B101K
Page 4 of 24
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