CY14B101K-SP25XCT CYPRESS [Cypress Semiconductor], CY14B101K-SP25XCT Datasheet - Page 18

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CY14B101K-SP25XCT

Manufacturer Part Number
CY14B101K-SP25XCT
Description
1 Mbit (128K x 8) nvSRAM With Real Time Clock
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Switching Waveforms
Figure 7
Figure 8
Document Number: 001-06401 Rev. *G
Note
28. HSB must remain HIGH during READ and WRITE cycles.
DQ (DATA OUT)
DQ (DATA OUT)
ADDRESS
ADDRESS
shows the SRAM Read Cycle 1(address controlled).
shows the SRAM Read Cycle 2 (CE and OE controlled).
OE
CE
ICC
STANDBY
t
OHA
Figure 7. SRAM Read Cycle 1
Figure 8. SRAM Read Cycle 2
t
PU
t
LZCE
t
AA
t
LZOE
t
ACE
t
DOE
[12, 13, 28]
t
RC
t
[12, 28]
RC
ACTIVE
DATA VALID
DATA VALID
t
HZOE
t
HZCE
t
PD
CY14B101K
Page 18 of 24
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