CY14B101K-SP25XCT CYPRESS [Cypress Semiconductor], CY14B101K-SP25XCT Datasheet - Page 13

• Manufacturer Part Number: CY14B101K-SP25XCT
• Description: 1 Mbit (128K x 8) nvSRAM With Real Time Clock
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4. Register Map Detail (continued)
Notes
Document Number: 001-06401 Rev. *G
5. W bit must be set to write to any of the RTC registers except the Flag register (0X1FFF1 to 0X1FFFF)
0x1FFF0
OSCF
WDF
CAL
AF
PF
W
R
Watchdog Timer Flag. This READ only bit is set to 1 when the watchdog timer is allowed to reach 0 without being
reset by the user. It is cleared to 0 when the Flags/Control register is READ.
Alarm Flag. This READ only bit is set to 1 when the time and date match the values stored in the alarm registers
with the match bits = 0. It is cleared when the Flags/Control register is READ.
Power Fail Flag. This READ only bit is set to 1 when power falls below the power fail threshold V
to 0 when the Flags/Control register is READ.
Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation.
This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip
does not clear this flag. This bit survives power cycles.
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power up.
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then WRITE them with
updated values. Setting the W bit to 0 causes the transfer of contents of the time registers to the timekeeping
counters. The W bit enables writes to RTC, Alarm, Calibration, Interrupt, and Flag registers.
READ Time. Setting the R bit to 1 copies a static image of the time keeping registers and places them in a holding
register. The user can then READ without concerns over changing values causing system errors. The R bit going
from 0 to 1 causes the time keeping capture, so the bit must be returned to 0 before reading again.
WDF
D7
D6
AF
D5
PF
OSCF
D4
Flags
D3
0
CAL
D2
D1
W
[5]
SWITCH
CY14B101K
. It is cleared
Page 13 of 24
D0
R
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