CY14B101K-SP45XC Cypress Semiconductor Corp, CY14B101K-SP45XC Datasheet
CY14B101K-SP45XC
Specifications of CY14B101K-SP45XC
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CY14B101K-SP45XC Summary of contents
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... SSOP package (ROHS compliant) ■ Functional Description The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory ...
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... Software Controlled STORE/RECALL Cycles ................ 21 Hardware STORE Cycle ................................................... 22 Soft Sequence Commands .............................................. 22 RTC Characteristics ......................................................... 23 Truth Table For SRAM Operations ................................. 23 Part Numbering Nomenclature ....................................... 24 Ordering Information ....................................................... 25 Package Diagrams ........................................................... 26 Document History Page ................................................... 27 Sales, Solutions, and Legal Information ........................ 29 Worldwide Sales and Design Support ......................... 29 Products ...................................................................... 29 CY14B101K Page [+] Feedback [+] Feedback ...
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... HIGH if not connected (connection optional). V Power Supply AutoStore™ Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM CAP to nonvolatile elements. Document Number: 001-06401 Rev. *J Figure 1. 48-Pin SSOP 48-SSOP 10 11 Top View 12 13 (Not To Scale Description CY14B101K HSB ...
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... See the “Truth Table For SRAM Operations” complete description of read and write modes. SRAM READ The CY14B101K performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A determines which of the 131,072 data bytes are 0-16 accessed ...
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... STORE, the WRITE is inhibited until a negative transition detected. This protects against inadvertent writes during power up or brownout conditions. Noise Considerations The CY14B101K is a high speed memory and must have a high frequency bypass capacitor of approximately 0.1 µF connected between V and possible ...
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... READ/WRITE Cycle Time. The worst case current consumption is shown for commercial temperature range, V chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY14B101K depends on the following items: The duty cycle of chip enable ■ ...
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... The six consecutive address locations are in the order listed HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes state depends on the state of OE. The I/O table shown is based on OE Low. ...
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... CY14B101K only sources current from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B101K. The battery capacity is chosen for total anticipated cumulative downtime required over the life of the system. ...
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... Clock accuracy depends on the quality of the crystal and calibration. The crystal oscillators typically have an error of +20ppm to +35ppm. However, CY14B101K employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5 seconds to -5 seconds per month ...
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... CC “AutoStore or Power Up RECALL” on page 20). Interrupts The CY14B101K has a Flags register, Interrupt register and Interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x1FFF6) ...
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... 10% (do not vary from this value and DQ in applications where undershoot exceeds -0.5V. Please see application note CY14B101K WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable INT AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low Page ...
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... Minutes Seconds Calibration (00000) WDT (000000) 0 H/L (1) P/L (0) Alarm Day Alarm Hours Alarm Minutes Alarm, Seconds Centuries OSCF 0 CAL (0) CY14B101K Function/Range D1 D0 Years: 00–99 Months: 01–12 Day of Month: 01–31 Day of Week: 01–07 Hours: 00–23 Minutes: 00–59 Seconds: 00–59 Calibration Values [7] Watchdog [7] ...
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... Time Keeping - Months 10s Month Time Keeping - Date 10s Day of Month Time Keeping - Day Time Keeping - Hours 10s Hours Time Keeping - Minutes 10s Minutes Time Keeping - Seconds 10s Seconds CY14B101K Years Months Day of Month Day of Week Hours Minutes Seconds Page [+] Feedback [+] Feedback ...
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... Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value. Document Number: 001-06401 Rev. *J Calibration/Control Calibration Sign WatchDog Timer WDT Interrupt Status/Control PFIE 0 H/L Alarm - Day 10s Alarm Date CY14B101K Calibration “Watchdog P Alarm Date Page [+] Feedback [+] Feedback ...
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... Set R bit resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults power up. Document Number: 001-06401 Rev. *J Alarm - Hours 10s Alarm Hours Alarm - Minutes Alarm - Seconds Time Keeping - Centuries Flags OSCF 0 CY14B101K Alarm Hours Alarm Minutes Alarm Seconds Centuries CAL cleared to SWITCH Page [+] Feedback ...
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... Inputs are static MHz V = Max, V < V < Max, V < V < > –2 mA OUT OUT Between V pin and rated CAP SS CY14B101K = 25°C) ................................................... 1.0W Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V –40°C to +85°C Min Max Commercial Industrial –1 +1 – 2 ...
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... T = 25° MHz 3 Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 7. AC Test Loads R1 577Ω 3.0V OUTPUT 789Ω CY14B101K Min Unit 20 Years 200 K Max Unit 48-SSOP Unit °C/W 34.85 ° ...
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... Device is continuously selected with CE and OE both Low. 13. Measured ±200 mV from steady state output voltage. 14. These parameters are guaranteed by design and are not tested. 15. HSB must remain HIGH during READ and WRITE cycles. Document Number: 001-06401 Rev Description Min Max CY14B101K Unit Min Max Min Max ...
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... IH Document Number: 001-06401 Rev. *J (continued Description Min Max SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE Figure 11. SRAM Write Cycle 2: CE Controlled SCE PWE t SD DATA VALID HIGH IMPEDANCE CY14B101K Unit Min Max Min Max [15, 17 LZWE t HA ...
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... If an SRAM Write does not taken place since the last nonvolatile cycle, no STORE takes place. 20. Industrial Grade Devices require 15 ms Max. Document Number: 001-06401 Rev. *J Min Commercial Industrial 150 Figure 12. AutoStore/Power Up RECALL t STORE t HRECALL . SWITCH CY14B101K CY14B101K Unit Max 2.65 V μs STORE occurs only No STORE occurs if a SRAM write ...
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... The six consecutive addresses are read in the order listed in the Document Number: 001-06401 Rev. *J [21, 22 Min Max 170 DATA VALID DATA VALID Table 2 on page HIGH during all six consecutive cycles. CY14B101K Unit Min Max Min Max 170 170 [22 STORE RECALL HIGH IMPEDANCE [22 STORE RECALL HIGH IMPEDANCE Page ...
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... Read and Write cycles in progress before HSB are given this amount of time to complete. Document Number: 001-06401 Rev. *J Description Min Figure 15. Hardware STORE Cycle Min Figure 16. Soft Sequence Processing CY14B101K CY14B101K Unit Max μ CY14B101K Unit Max μs 70 [22, 24] Page [+] Feedback [+] Feedback ...
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... Document Number: 001-06401 Rev. *J Test Conditions At Min Temperature from Power up or Enable At 25°C Temperature from Power up or Enable Mode Deselect/Power down –DQ ); Read 0 7 Output Disabled –DQ ); Write 0 7 CY14B101K Min Max Unit Commercial 300 nA Industrial 350 nA 1.8 3.3 V 1.2 2 ...
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... Pb-Free NVSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Document Number: 001-06401 Rev. *J Option Tape and Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (–40 to 85°C) Package SSOP Data Bus RTC Voltage 3.0V CY14B101K Speed Density: 101 - 1 Mb Page [+] Feedback [+] Feedback ...
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... CY14B101K-SP25XC CY14B101K-SP25XCT CY14B101K-SP25XI CY14B101K-SP25XIT 35 CY14B101K-SP35XC CY14B101K-SP35XCT CY14B101K-SP35XI CY14B101K-SP35XIT 45 CY14B101K-SP45XC CY14B101K-SP45XCT CY14B101K-SP45XI CY14B101K-SP45XIT All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Document Number: 001-06401 Rev. *J Package Package Type Diagram 51-85061 48-pin SSOP 51-85061 48-pin SSOP ...
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... Package Diagrams Figure 17. 48-Pin Shrunk Small Outline Package (51-85061) Document Number: 001-06401 Rev. *J CY14B101K 51-85061-*C Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. ECN NO. Orig. of Change ** 425138 TUP *A 437321 TUP *B 471966 TUP *C 503272 PCI *D 597002 TUP *E 688776 VKN *F 1349963 UHA/SFV *G 1739984 vsutmp8/AESA *H 2427986 GVCH/PYRS Document Number: 001-06401 Rev. *J ...
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... Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 REV. ECN NO. Orig. of Change *I 2663934 GVCH/PYRS *J 2815609 GVCH Document Number: 001-06401 Rev. *J Submission Description of Change Date 02/24/09 Updated Features Updated pin definition of WE Removed AutoStore enable/disable section Added Best practices Updated “ ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06401 Rev. *J AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised November 26, 2009 CY14B101K Page [+] Feedback [+] Feedback ...