CY14B101K-SP25XCT CYPRESS [Cypress Semiconductor], CY14B101K-SP25XCT Datasheet
CY14B101K-SP25XCT
Related parts for CY14B101K-SP25XCT
CY14B101K-SP25XCT Summary of contents
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... Document Number: 001-06401 Rev Mbit (128K x 8) nvSRAM With Real Time Clock Functional Description The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap™ technology producing the world’s most reliable nonvolatile memory ...
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... Top View 12 13 (Not To Scale Description Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM CY14B101K HSB ...
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... IO lines left LOW, internal circuitry turns off the output buffers t goes LOW. AutoStore Operation The CY14B101K stores data to nvSRAM using one of three storage operations: 1. Hardware Store activated by HSB 2. Software Store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101K ...
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... detected. This protects against inadvertent writes during power up or brownout conditions. Noise Considerations The CY14B101K is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 µF connected between V are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise ...
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... The six consecutive address locations are in the order listed HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes state depends on the state of OE. The IO table shown is based on OE Low. ...
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... Setting the Clock Setting the WRITE bit ‘W’ (in the flags register at 0x1FFF0 and READ/WRITE ‘1’ halts updates to the CY14B101K registers. The correct day, CC date, and time are then written into the registers in 24 hour BCD format. The time written is referred to as the ‘Base Time’. This value is stored in nonvolatile registers and used in calculation of the current time. Resetting the WRITE bit to ‘ ...
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... Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up battery is used, use a 3V lithium and the CY14B101K only source current from the battery when the primary power is removed. However, the battery does not recharge at any time by the CY14B101K ...
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... Register Watchdog Register Power Monitor The CY14B101K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low V access. The power monitor is based on an internal band gap ...
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... The processor either polls this register or enables to inform interrupts when a flag is set. The flags are automatically reset once the register is READ. Recommended Values Y1 = 32.768 KHz MΩ Figure 6. Interrupt Block Diagram WDF WIE PF PFE AF AIE CY14B101K V P/L CC Pin INT Driver H Page [+] Feedback ...
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... 10s Month Time Keeping – Date 10s Day of Month Time Keeping – Day CY14B101K Function/Range D0 Years: 00 – 99 Months: 01 – 12 Day of Month: 01 – 31 Day of week: 01 – 07 Hours: 00 – 23 Minutes: 00 – 59 Seconds: 00 – 59 [4] Calibration Values [4] Watchdog [4] 0 Interrupts Alarm, Day of Month: 01 – ...
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... D4 D3 10s Hours Time Keeping – Minutes 10s Minutes Time Keeping – Seconds 10s Seconds Calibration/Control Calibration Sign WatchDog Timer WDT CY14B101K Hours Minutes Seconds Calibration “Watchdog Timer” on page 7. Page ...
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... Alarm – Hours 10s Alarm Hours Alarm – Minutes 10s Alarm Minutes Alarm – Seconds 10s Alarm Seconds Time Keeping – Centuries 10s Centuries CY14B101K P Alarm Date Alarm Hours Alarm Minutes D2 ...
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... Notes 5. W bit must be set to write to any of the RTC registers except the Flag register (0X1FFF1 to 0X1FFFF) Document Number: 001-06401 Rev. *G Flags OSCF 0 CY14B101K CAL cleared SWITCH [5] Page ...
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... V < Max, V < V < > –2 mA OUT = 4 mA OUT pin and rated CAP SS CY14B101K = 25°C) ................................................... 1.0W [6] .................................... 15 mA Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V Min Max ns ...
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... MHz 3 Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 3.0V OUTPUT 789Ω CY14B101K Max Unit 48-SSOP Unit °C/W TBD °C/W TBD R1 577Ω ...
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... Max CY14B101K Unit Max 20 ms 12.5 ms 2.65 V μs Page [+] Feedback ...
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... Enable at 25°C Temperature from Power Up or Enable at Min Temperature from Power Up or Enable at 25°C Temperature from Power Up or Enable “Mode Selection” on page 5. WE must be HIGH during all six consecutive cycles. CY14B101K 45 ns Part Unit Max Min Max ...
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... HSB must remain HIGH during READ and WRITE cycles. Document Number: 001-06401 Rev. *G [12, 13, 28] Figure 7. SRAM Read Cycle OHA DATA VALID [12, 28] Figure 8. SRAM Read Cycle ACE t LZCE t DOE t LZOE t ACTIVE PU CY14B101K HZCE t HZOE DATA VALID Page [+] Feedback ...
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... Document Number: 001-06401 Rev. *G [28, 29] Figure 9. SRAM WRITE Cycle SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE [28, 29] Figure 10. SRAM WRITE Cycle SCE PWE t SD DATA VALID HIGH IMPEDANCE CY14B101K LZWE Page [+] Feedback ...
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... GHAX t GLAX OE DATA VALID DQ (DATA) Document Number: 001-06401 Rev. *G Figure 11. AutoStore/Power Up RECALL t STORE t HRECALL t RC ADDRESS # 6 CY14B101K STORE occurs only No STORE occurs without atleast one if a SRAM write has happened SRAM write t STORE “Mode Selection” on page STORE RECALL ...
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... Document Number: 001-06401 Rev ADDRESS # 6 DATA VALID Figure 14. Hardware STORE Cycle t STORE t DELAY Figure 15. Soft Sequence Processing 34 Soft Sequence Command t SS ADDRESS # 1 ADDRESS # 6 CY14B101K “Mode Selection” on page STORE RECALL HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID ADDRESS # 6 Page [+] Feedback ...
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... AutoStore + Software Store + Hardware Store Cypress Document Number: 001-06401 Rev. *G Option Tape and Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (–40 to 85°C) Package SSOP Data Bus RTC Voltage 3.0V CY14B101K Speed Density: 101 - 1 Mb Page [+] Feedback ...
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... Ordering Information All mentioned parts are Pb-free. Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts. Speed (ns) Ordering Code 25 CY14B101K-SP25XCT CY14B101K-SP25XC 25 CY14B101K-SP25XIT CY14B101K-SP25XI 35 CY14B101K-SP35XCT CY14B101K-SP35XC 35 CY14B101K-SP35XIT CY14B101K-SP35XI 45 CY14B101K-SP45XCT CY14B101K-SP45XC 45 CY14B101K-SP45XIT CY14B101K-SP45XI Package Diagram Figure 16. 48-Pin Shrunk Small Outline Package, 51-85061 Document Number: 001-06401 Rev ...
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... Document History Page Document Title: CY14B101K 1 Mbit (128K x 8) nvSRAM With Real Time Clock Document Number: 001-06401 Issue REV. ECN NO. Orig. of Change Date ** 425138 See ECN TUP *A 437321 See ECN TUP *B 471966 See ECN TUP *C 503272 See ECN PCI *D 597002 See ECN ...