HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 465

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Retransmission by the SCI in Transmit Mode: Figure 15.10 shows the retransmission operation
in the SCI transmit mode.
1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a
2. The TEND bit in SCSSR is not set in the frame that received the error signal that indicated the
3. The FER/ERS bit in SCSSR is not set when no error signal is returned from the receiving side.
4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1
Support for Block Transfer Mode :
This smart card interface conforms to the T = 0 (character transfer) protocols of ISO/IEC7816-3.
As a result, this smart card interface does not support block transfer, in which error signals are
neither sent nor detected, and data is not automatically retransmitted.
error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time,
an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is
sampled.
error.
when the transmission of the frame that includes the retransmission is considered completed. If
the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested.
Notes: 1.
TEND
FER/ERS
Ds
TDRE
Transfer from TDR to TRS
D0
D1
2.
3.
4.
D2
This portion corresponds to the above explanation 1.
This portion corresponds to the above explanation 2.
This portion corresponds to the above explanation 3.
This portion corresponds to the above explanation 4.
nth transfer frame
D3
D4
Figure 15.10 Retransmission in SCI Transmit Mode
D5
D6
D7
Dp DE
*
1
*
2
Ds
Transfer from TDR to TRS
D0
D1
D2
Retransmitted frame
D3
D4
D5
D6
D7
Rev. 4.00, 03/04, page 419 of 660
Dp
*
3
(DE)
*
4
Ds
Transfer from
TDR to TRS
D0
Transfer frame n + 1
D1
D2
D3
D4