HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 431

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
Figure 14.14 shows SCI transmission in the multiprocessor format.
that the SCTDR contains new data, and loads this data from the SCTDR into the SCTSR.
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is
transmitted in the following order from the TxD0 pin:
A. Start bit: One 0 bit is output.
B. Transmit data: Seven or eight bits are output, LSB first.
C. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
D. Stop bit: One or two 1 bits (stop bits) are output.
E. Marking: Output of 1 bits continues until the start bit of the next transmit data.
from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit,
then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit
(TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
Example: 8-bit data with multiprocessor bit and one stop bit
TXI interrupt
generated
TDRE
TEND
Serial
request
data
1
Start
bit
0
clears TDRE bit to 0
cessing routine and
Figure 14.14 SCI Multiprocessor Transmit Operation
TDR with the TXI
Writes data to
interrupt pro-
D 0
D 1
1 frame
Data
D 7
processor
TXI interrupt
generated
Multi-
request
bit
0/1
Stop
bit
1
Start
bit
0
D 0
D 1
Rev. 4.00, 03/04, page 385 of 660
Data
D 7
processor
Multi-
0/1
bit
TEI interrupt
generated
request
Stop
bit
1
(marking)
Idling
1