HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 42

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Section 3 Memory Management Unit (MMU)
Table 3.1
Section 4 Exception Processing
Table 4.1
Table 4.2
Table 4.3
Section 5 Cache
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Section 7 User Break Controller
Table 7.1
Rev. 4.00, 03/04, page xlii of xlvi
Initial Register Values ................................................................................................ 15
Addressing Modes and Effective Addresses............................................................... 23
Instruction Formats ..................................................................................................... 27
Classification of Instructions ...................................................................................... 30
Data Transfer Instructions........................................................................................... 34
Arithmetic Instructions ............................................................................................... 36
Logic Operation Instructions ...................................................................................... 39
Shift Instructions......................................................................................................... 40
Branch Instructions ..................................................................................................... 41
Access States Designated by D, C, and PR Bits ......................................................... 64
Exception Event Vectors............................................................................................. 82
Exception Codes ......................................................................................................... 85
Types of Reset ............................................................................................................ 91
LRU and Way Replacement ..................................................................................... 100
Way to be Replaced when Cache Miss Occurs during PREF
Instruction Execution................................................................................................ 103
Way to be Replaced when Cache Miss Occurs during Execution of
Instruction other than PREF Instruction ................................................................... 103
LRU and Way Replacement (when W2LOCK=1) ................................................... 103
LRU and Way Replacement (when W3LOCK=1) ................................................... 104
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)....................... 104
Pin Configuration...................................................................................................... 113
IRL3 to IRL0 Pins and Interrupt Levels ................................................................... 115
Interrupt Exception Handling Sources and Priority (IRQ Mode) ............................. 117
Interrupt Exception Handling Sources and Priority (IRL Mode).............................. 119
Interrupt Level and INTEVT Code........................................................................... 120
Interrupt Request Sources and IPRA to IPRE........................................................... 121
Interrupt Response Time........................................................................................... 132
Data Access Cycle Addresses and Operand Size Comparison Conditions............... 149
System Control Instructions.................................................................................... 42
Instruction Code Map ............................................................................................. 46
Tables