HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 304

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

On-Chip Peripheral Module Request: In this mode a transfer is performed at the transfer request
signal (interrupt request signal) of an on-chip peripheral module. This mode cannot be set in case
of 16-byte transfer. The transfer request signals include 4 signals: the receive data full interrupts
(RXI) and the transmit data empty interrupts (TXI) from serial communication interfaces (SCIF),
the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer
interrupt (CMI) of the CMT. When this mode is selected, if the DMA transfer is enabled (DE = 1,
DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request
signal. The source of the transfer request does not have to be the data transfer source or
destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's
receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source
must be the SCI's transmit data register (TDR). And if the transfer requester is the A/D converter,
the data transfer source must be the A/D data register (ADDR).
Table 9.3
ADDR: A/D data register of A/D converter
Note:
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not generated to the CPU.
The DMA transfer request signals of table 9.3 are automatically withdrawn when the
corresponding DMA transfer is performed. If the cycle-steal mode is being used, they are
withdrawn at the first transfer; if the burst mode is being used, they are withdrawn at the last
transfer.
Rev. 4.00, 03/04, page 258 of 660
RS3 RS2
1
1
1
1
1
1
0
0
1
1
1
1
* External memory, memory-mapped external device, on-chip peripheral module
(excluding DMAC, UBC , and BSC)
RS1
1
1
0
0
1
1
Selecting On-Chip Peripheral Module Request Modes with the RS Bit
RS0
0
1
0
1
0
1
DMA
Transfer
Request
Source
SCIF
transmitter
SCIF
receiver
A/D
converter
CMT
DMA Transfer Request Signal Source
TXI2 (SCIF transmit data empty
interrupt transfer request)
RXI2 (SCIF receive data full
interrupt transfer request)
ADI (A/D conversion end
interrupt)
CMI (Compare match timer
interrupt)
Any*
RDR1
ADDR
Any*
Desti-
nation Bus Mode
TDR2
Any*
Any*
Any*
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal