HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 327

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel's DMATCR is 0, or when the DE bit of the channel's CHCR is cleared to
0.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the
NMIF or AE bit in the DMAOR is set to 1, or when the DME bit in the DMAOR is cleared to 0.
When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt
enable) bit has been set, a DMAC interrupt (DEI) is requested to the CPU. This transfer ending
does not apply to conditions in (a) to (d) described above.
When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel's CHCR. The TE bit is not set when this happens. This transfer ending does not apply
to conditions in (a) to (d) described above.
Transfers ending when the AE bit or NMIF bit is set to 1 in DMAOR: When an NMI interrupt
occurs, the AE bit or NMIF bit is set to 1 in the DMAOR and all channels stop their transfers
according to the conditions in (a) to (d) described above, and pass the bus right to other bus
masters. Consequently, even if the AE bit or NMI bit is set to 1 during transfer, the SAR, DAR,
DMATCR are updated. The TE bit is not set. To resume the transfers after DMAC address
error exception handling or NMI interrupt exception handling, clear the AE or NMIF bit to 0.
At this time, if there are channels that should not be restarted, clear the corresponding DE bit in
the CHCR.
Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the
DMAOR forcibly stops the transfers on all channels. The TE bit is not set. All channels stop
their transfers according to the conditions in (a) to (d) in 9.4.7, DMA Transfer Ending
Conditions, as in DMAC address error occurrence or NMI interrupt generation. In this case, the
values in SAR, DAR, and DMATCR are also updated.
Rev. 4.00, 03/04, page 281 of 660