HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 326

no-image

HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417706
Manufacturer:
TDK
Quantity:
500
Part Number:
HD6417706
Manufacturer:
TOSH
Quantity:
1 000
Part Number:
HD6417706-SH3-133V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417706BP133
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417706BP133V
Manufacturer:
HITACHI/日立
Quantity:
20 000
Part Number:
HD6417706F120DV
Manufacturer:
HITACHI
Quantity:
96
Part Number:
HD6417706F120DV
Manufacturer:
RENESAS/PBF
Quantity:
375
Part Number:
HD6417706F120DV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417706F133
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417706F133V
Manufacturer:
EDISON
Quantity:
2 000
Part Number:
HD6417706F133V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD6417706F133V
Quantity:
27
9.4.7
The DMA transfer ending conditions vary for individual channels ending and all channels ending
together. At transfer end, the following conditions are applied except the case where the value set
in the DMATCR reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto request)
(b) Burst mode, edge detection (external request, internal request, and auto request)
(c) Burst mode, level detection (external request)
(d) Bus timing when transfers are suspended
Rev. 4.00, 03/04, page 280 of 660
When the transfer ending conditions are satisfied, DMAC transfer request acceptance is
suspended. The DMAC stops operating after completing the number of transfers that it has
accepted until the ending conditions are satisfied.
In the cycle-steal mode, the operation is the same regardless of whether the transfer request is
detected by the level or at the edge.
The timing from the point where the ending conditions are satisfied to the point where the
DMAC stops operating differs from that in cycle steal mode. In the edge detection in the burst
mode, though only one transfer request is generated to start up the DMAC, stop request
sampling is performed in the same timing as transfer request sampling in the cycle-steal mode.
As a result, the period when stop request is not sampled is regarded as the period when transfer
request is generated, and after performing the DMA transfer for this period, the DMAC stops
operating.
Same as described in (a).
The transfer is suspended when one transfer ends. Even if transfer ending conditions are
satisfied during read in the direct address transfer in the dual address mode, the subsequent
write process is executed, and after the transfer in (a) to (c) above has been executed, DMAC
operation suspends.
DMA Transfer Ending Conditions

Related parts for HD6417706