DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 8

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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TOL
V
V
I
R
V
R
ΔR
t
t
t
t
t
t
IN
JIT
OS
LTR
LTF
LTRFMM
LTDE
Symbol
Symbol
Symbol
Symbol
ID
IN
LTOD
IT
LTOT
CML Input Timing Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
CML Input Electrical Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
CML Retimed Loop Through Output Electrical Specifications, DS32ELX0124
Only
Over recommended operating supply and temperature ranges unless otherwise specified.
CML Retimed Loop Through Output Timing Specifications, DS32ELX0124
Only
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical and Timing Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Parameter is guaranteed by characterization and is not tested at production.
LTOT
JIT
Serial Input Jitter Tolerance
Differential input voltage
Single ended input voltage
Input Current
Input Termination
Output differential voltage
Output termination
Mismatch in output termination resistors
Additive Output Jitter
Output Overshoot
Retimed output driver differential low to high
transition time
Retimed output driver differential high to low
transition time
Mismatch in Rise/Fall Time
Retimed driver de-emphasis width
Parameter
Parameter
Parameter
Parameter
RJ = 0.18 UI
DJ = 0.37 UI
SJ increased until failure
1.25 Gbps
f < 10 kHz
f > 1 MHz
2.5 Gbps
f < 10 kHz
f > 1 MHz
3.125 Gbps
f < 10 kHz
f > 1 MHz
(Note
(Note
VOD_CTRL resistor = 9.09 kΩ
(Note
50Ω
75Ω
(Note
(Note
(Note
(Note
(Note
8
3)
3)
3)
3)
3)
3)
3)
3)
Conditions
Conditions
Conditions
Conditions
(Note
(Note
(Note
(Note
2,
2,
2,
2,
-300
1.15
Note
Note
Note
Note
Min
Min
230
115
Min
Min
84
40
60
5)
5)
5)
5)
Typ
Typ
Typ
Typ
100
0.5
0.3
0.3
1.5
30
50
70
50
75
24
74
74
5
5
1
2200
1100
Max
Max
Max
1.45
Max
116
105
105
50
60
90
35
15
8
Units
Units
Units
Units
mV
mV
μA
UI
ps
ps
ps
UI
%
%
%
Ω
V
Ω