DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 13

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

50mV and can be DC-coupled where there is no significant
Ground potential difference between the interfacing systems.
The serial inputs also provides input equalization control in
order to compensate for loss from the media. The level of
equalization is controlled by the SMBus interface. For the
DS32ELX0124, each input can have its own independent
equalizer settings.
It is recommended to use RxIN0+/- as the primary input. Due
to its close proximity to the loop through driver, RxIN1 has a
typical performance less than RxIN0, with regards to cable
length performance. When interfacing to RxIN1+/- and trans-
mitting with the loop through driver on TxOUT+/-, it is impor-
tant to follow good layout practices as described in the layout
guidelines section and in the LVDS Owner’s Manual. Poor
layout techniques can result in excessive cross talk coupled
into RxIN1.
CML OUTPUT INTERFACING (DS32ELX0124 ONLY)
The retimed loop through serial outputs of the DS32ELX0124
provide low-skew differential signals. Internal resistors con-
nected from TxOUT+ and TxOUT- to VDD25 terminate the
outputs. The output level can be set by adjusting the pull-
down resistor to the VOD_CTRL pin. The output terminations
can also be programmed to be either 50 or 75 ohms.
The output buffer consists of a current mode logic(CML) driver
with user configurable de-emphasis control, which can be
used to optimize performance over a wide range of transmis-
sion line lengths and attenuation distortions resulting from low
cost CAT(-5, -6, -7) cable or FR4 backplane. Output de-em-
phasis is user programmable through SMBus interface. Users
can control the strength of the de-emphasis to optimize for a
specific system environment. Please see the Register Map,
register 67'h bits 6:5, for details.
DEVICE CONFIGURATION
There are four ways to configure the DS32EL0124 and
DS32ELX0124 devices, these combinations are shown in
Table
RS and DC_B pins change the link startup behavior of the
deserializers. When connecting to a serializer other than the
DS32EL0421 or DS32ELX0421, Remote Sense should be
disabled. The descrambler and NRZI decoder shown in
1
0
0
1
1
can be enabled or disabled through register programming.
Remote Sense Pin (RS)
1. Refer to
Figure 7
to see how the combinations of the
0
1
0
1
DC-Balance Pin(DC_B)
TABLE 1. Device Configuration Table
Table
13
Remote Sense enabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder disabled by default
Remote Sense enabled
DC-Balance disabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
Remote Sense disabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
Remote Sense disabled
DC-Balance disabled
No Data Alignment
De-Scrambler and NRZI decoder disabled by default
When Remote Sense is enabled, with RS pin tied low, the
deserializer must be connected directly to a DS32EL0421/
DS32ELX0421 serializer without any active components be-
tween them. The Remote Sense module features both an
upstream and downstream communication method for the
serializer to detect a deserializer and vice versa. This feature
is used to pass link status information between the 2 devices.
If DC-Balance is enabled, the maximum number of parallel
LVDS lanes is four. The fifth lane becomes a Data Valid signal
(TXIN4±). If the Data Valid input to the serializer is logic high,
then SYNC characters are transmitted. If the deserializer re-
ceives a SYNC character, then the LVDS data outputs will all
be logic low and the Data Valid outputs will be logic high. If
the deserializer detects a DC-Balance code error, the output
data pins will be set to logic high with the Data Valid output
also set to logic high.
In the case where DC-Balance is enabled and Remote Sense
is disabled, with RS set to high and DC_B set to low, an ex-
ternal device should toggle the Data Valid input to the serial-
izer periodically to ensure constant lock. With these pin
settings the devices can interface with other active compo-
nent in the high speed signal path, such as fiber modules.
Every time a DS32EL0421/DS32ELX0421 serializer estab-
lishes a link to a DS32EL0124/DS32ELX0124 deserializer
with DC-Balance enabled and Remote Sense disabled, the
Data Valid input to the serializer must be held high for 110
LVDS clock periods. This allows the deserializer to extract the
clock and perform lane alignment while skipping the LINK
ACQUISITION state.
When both Remote Sense and DC-Balance are disabled,
RS and DC_B pins set to high, the LVDS lane alignment is
not maintained. In this configuration, data formatting is han-
dled by an FPGA or external source. In this mode the dese-
rializer locks to incoming random data. To achieve lock during
the clock acquisition phase, the incoming data should have a
transition density of approximately 20% for a period of 200 µs.
Scrambling and NRZI encoding can be implemented to help
improve the transition density of the data. This pin setting also
allows for the devices to interface with other active compo-
nents in the high speed signal path.
Configuration
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