DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 22

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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Addr (Hex)
06
07 — 1F Reserved
20
21
22
23 — 26 Reserved
GP Out
Device Config 0
Device Config 1
Device Config Override
Name
Bits
7:3
2
1
0
7
6:3
2
1
0
7
6
5
4
3
2
1:0
7
6
5
4
3
2
1
0
Reserved
GP Out 2
GP Out 1
GP Out 0
LVDS Always On Clock
Reserved
Reverse Data Order
Reset Channel
Digital Power Down
Reserved
NRZI Decode Enable
Descramble Enable
Rx Mux
Decode Bypass
Training Sequence Enable R/W 0
Device Configuartion
Reserved
NRZ Override
Descramble Override
Rx Mux Override
Reserved
Decode Bypass Override
Traning Override
Device Config Override
Field
22
R/W Default
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
0
0
0
0
0
Output value on GPIO2
Output value on GPIO1
Output value on GPIO0
1: Disable
0: When not locked switch to Always
On Clock
0: Normal
1: Reverse output data order
Reset input high speed channel
Power down parallel, seria-to-
parallell, and always on clock
Enable NRZI decoding of incoming
data; requires an override bit
Enabled the descrambler, requires an
override bit
RX_MUX_SEL control register.
requires an override bit
Bypass DC Balance decoder.
requires an override bit
Enable training sequence. requires
an override bit
MSB: Remote Sense enable, active
low
LSB: DC balance encoder enable,
active low
requires an override bit
Unlock bit 6 of register 21'h
Unlock bit 5 of register 21'h
Unlock bit 4 of register 21'h
Unlock bit 3 of register 21'h
Unlock bit 2 of register 21'h
Unlock bits 1 and 0 of register 21'h
Description