DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 24

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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Addr (Hex)
30 — 3A Reserved
3B
3C
3D
3E
3F
40 — 49 Reserved
49
60
Data Rate
Reserved
Event Status
Error Status LSBs
Errors Status MSBs
Loop Through Driver Config 7:5
EQ Attenuator
Name
Bits
7
6:4
3:2
1
0
7:0
7:0
7:0
4
3:1
0
7:4
3
2
1
0
Reserved
Frequency Range
BIST Status
BIST Done
BIST Allign Done
Event Count
Data Error Count
Data Error Count
Reserved
Termination Select
Output Amplitude Adjust
Reserved
Reserved
Attenuator 0 Override
Attenuator 1 Override
Attenuator 0 Enable
Attenuator 1 Enable
Field
24
R/W Default
R
R
R
R
R
R
R
R/W 1
R/W 011'b
R/W 0
R/W 0
R/W 0
R/W 0
0
111'b
0
0
0
0
0
0
0
0
0
001: Reserved
010: 1 — 1.3 Gbps
011: 1.2 — 1.8 Gbps
100: 1.5 — 2.1 Gbps
101: 1.9 — 2.7 Gbps
110: 2.4 — 3.2 Gbps
111: No Lock
00: BIST passed
01: BIST failed to capture
PREAMBLE
10: BIST pattern mode failed
11: BIST data sequence failed
BIST pattern done. Set when not
using repeat.
Alignment of incoming data done
Count of errors that caused a loss of
link
Number of errors in data — LSB
Number of errors in data — MSB
0: 75Ω
1: 50 Ω
000: Level 7
001: Level 8 (Highest output)
010: Level 5
011: Level 6 (Normal output)
100: Level 4
101: Level 3
110: Level 2
111: Level 1 (Lowest output)
Overrides attenuation control in EQ 0
Overrides attenuation control in EQ 1
1: enables attenuatorfor for EQ 0.
Requires bit 3 to be set
Enables attenuato for EQ 1. Requires
bit 2 to be set.r
Description