DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 4

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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Pin Name
Control Pins
LT_EN
RX_MUX_SEL 12
VOD_CTRL
DC_B
RS
RESET
LOCK
SMBus
SCK
SDA
SMB_CS
Other
GPIO0
GPIO1
GPIO2
NC
Pin Number
2
14
5
6
30
31
I, SMBus
I/O, SMBus
I, SMBus
3
4
11
2 ,8, 9, 10, 12, 13, 14, 19,
20, 21, 22, 23, 24, 29
8, 9, 10, 13, 23, 24, 29
I/O, Type
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
O, LVCMOS
33
32
34
I/O, LVCMOS Software configurable IO pins.
I/O, LVCMOS Software configurable IO pins.
I/O, LVCMOS Software configurable IO pins.
Misc.
Misc
Description
DS32ELX0124 only. When held high, retimed serialized high speed
output is enabled.
DS32ELX0124 only. RX_MUX_SEL selects the input of the deserializer.
0 = RxIN0+/- selected
1 = RxIN1+/- selected
DS32ELX0124 only. VOD control. The deserializer loop through output
amplitude can be adjusted by connecting this pin to a pull-down resistor.
The value of the pull-down resistor determines the VOD. See
THROUGH DRIVER LAUNCH AMPLITUDE
DC-balance and Remote Sense pins. See Application section for device
behavior.
Reset pin. When held low, reset the device.
0 = Device Reset
1 = Normal operation
Lock indication output. pin goes low when the deserializer is locked to the
incoming data stream and begins to output data and clock on RxOUT and
RxCLKOUT respectively.
0 = Deserializer locked
1 = Deserializer not locked
SMBus compatible clock.
SMBus compatible data line.
SMBus chip select. When held high, SMBus management control is
enabled.
No Connect, for DS32EL0124
No Connect, for DS32ELX0124
4
for more details.
LOOP