DS32EL0124SQ NSC [National Semiconductor], DS32EL0124SQ Datasheet - Page 12

• Manufacturer Part Number: DS32EL0124SQ
• Description: 125 MHz- 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface
• Manufacturer: NSC [National Semiconductor]

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DESCRAMBLER AND NRZI DECODER
The CDR of the deserializer expects a transition density of
20% for a period of 200 μs. To improve the transition density
of the data, the scrambler and NRZI encoder, which are inte-
grated features in the DS32EL0421 and DS32ELX0421, se-
rializers can be enabled. If the descrambler is enabled, the
serialized data is descrambled after being recovered by the
CDR to according to the polynomial specified in the
DS32EL0421 datasheet. Using the scrambler/descrambler
helps to lower EMI emissions by spreading the spectrum of
the data. Scrambling also creates transitions for a
deserializer’s CDR to properly lock onto.
The scrambler is enabled or disabled by default depending
on how the DC_B and RS pins are configured. To override
the default scrambler setting two register writes must be per-
FIGURE 7. Deserializer State Diagram
12
formed. First, write to register 22’h and set bit 5 to unlock the
descrambler register. Next write to register 21’h and change
bit 5 to the desired value. Please note that NRZI decoder has
its own control bits in registers 22'h and 21'h.
CML INPUT INTERFACING
The DS32ELX0124 has two inputs to support redundancy
and failover applications. Either input can be selected by us-
ing the RX_MUX_SEL pin or internal control registers.
Whichever input is selected will be routed to the CDR of the
deserializer. Only one input may be selected at a time.
The input stage is self-biased and does not need any external
bias circuitry. The DS32EL0124 and DS32ELX0124 include
integrated input termination resistors. These deserializers al-
so support a wide common mode input from 50mV to Vcc -
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