ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 7

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12, 13
14
15
16
17
18
19
20
21
Mnemonic
CLK
DATA
LE
CE
SW
V
CP
CP
AV
RF
RF
A
RF
RF
AV
PDB
DV
REF
LD
MUXOUT
P
GND
IN
IN
OUT
OUT
OUT
GND
DD
DD
DD
IN
+
−
RF
1
2
−
+
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.
Charge Pump Power Supply. This pin should be greater than or equal to AV
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Charge Pump Output. When enabled, this provides ±I
is connected to V
Charge Pump Ground. This is the ground return pin for CP
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AV
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
Analog Ground. This is a ground return pin for AV
Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
RF Output. The output level is programmable. The VCO fundamental output or a divided down version is
available.
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AV
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
Digital Power Supply. This pin should be the same voltage as AV
plane as close as possible to this pin.
Reference Input. This is a CMOS input with a nominal threshold of V
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of
PLL lock.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
TUNE
to drive the external VCO.
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE
DATA
CLK
SW
THAT MUST BE CONNECTED TO GND.
CE
LE
V
P
1
2
3
4
5
6
Figure 3. Pin Configuration
Rev. 0 | Page 7 of 28
(Not to Scale)
ADF4150
TOP VIEW
PIN 1
INDICATOR
18
17
16
15
14
13
DV
PDB
AV
RF
RF
A
DD
DD
DD
GND
1 and AV
OUT
OUT
DD
DD
2 must have the same value as DV
RF
must have the same value as DV
2
CP
+
−
to the external loop filter. The output of the loop filter
OUT
DD
.
2.
DD
. Place decoupling capacitors to the ground
DD
/2 and a dc equivalent input resistance
DD
. In systems where AV
DD
DD
.
.
ADF4150
DD
is 3 V, it