ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 4

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ADF4150

Manufacturer Part Number
ADF4150
Description
Fractional-N/Integer-N PLL Synthesizer
Manufacturer
AD [Analog Devices]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4150BCPZ-RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Parameter
RF OUTPUT CHARACTERISTICS
NOISE CHARACTERISTICS
1
2
3
4
5
6
ADF4150
AC coupling ensures AV
T
Using a tuned load.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (F
and at a frequency offset (f) is given by PN = P
Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.
A
Minimum Output Frequency Using RF
Maximum RF
Harmonic Content (Second)
Harmonic Content (Third)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power
Output Power Variation
Level of Signal With RF Mute Enabled
Spurious Signals Due to PFD
Frequency
Normalized Phase Noise Floor
Normalized 1/f Noise (PN
Normalized Phase Noise Floor
Normalized 1/f Noise (PN
= 25°C; AV
Output Dividers
Output Dividers
(PN
(PN
SYNTH
SYNTH
DD
)
)
6
4
4
= DV
IN
PFD
3
Frequency Using RF
DD
. PN
= 3.3 V; prescaler = 8/9; f
DD
SYNTH
/2 bias.
= PN
1_f
1_f
)
)
TOT
5
5
− 10logF
1_f
+ 10log(10 kHz/f) + 20log(F
PFD
REFIN
− 20logN.
= 100 MHz; f
Min
31.25
B Version
PFD
= 26 MHz; f
Typ
−19
−13
−20
−10
−4
+5
±1
−40
−223
−123
−222
−119
−90
−75
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
Rev. 0 | Page 4 of 28
RF
= 1.7422 GHz.
Max
4400
Unit
MHz
MHz
dBc
dBc
dBc
dBc
dBm
dBm
dB
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
Conditions/Comments
500 MHz VCO input and divide-by-16 selected
Fundamental VCO output
Fundamental VCO output
Divided VCO output
Divided VCO output
Maximum setting
Minimum setting
PLL loop BW = 500 kHz (ABP = 3 ns)
10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns)
PLL loop BW = 500 kHz (ABP = 6 ns); low noise
mode selected
10 kHz offset; normalized to 1 GHz; (ABP = 6 ns);
low noise mode selected
VCO output
RF output buffers
RF
)

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