ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 20

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4150
REGISTER 3
Control Bits
With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed.
Figure 23 shows the input data format for programming
this register.
Antibacklash Pulse Width
Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns.
This is the recommended mode for fractional-N use. By setting
this bit to 1, the 3 ns pulse width is used and results in a phase
noise and spur improvement in integer-N operation. For
fractional-N mode it is not recommended to use this smaller
setting.
Charge Cancellation Mode Pulse Width
Setting DB21 to 1 enables charge pump charge cancellation.
This has the effect of reducing PFD spurs in integer-N mode.
In fractional-N mode, this bit should not be used and the
relevant result in a phase noise and spur improvement. For
fractional-N mode, it is not recommended to use this smaller
setting.
Cycle Slip Reduction (CSR) Enable
Setting DB18 to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the phase fre-
quency detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge pump current setting must also
be set to a minimum. See the Cycle Slip Reduction for Faster
Lock Times section for more information.
Clock Divider Mode
Bits[DB16:DB15] must be set to 1, 0 to activate PHASE resync
or 0, 1 to activate fast lock. Setting Bits[DB16:DB15] to 0, 0
disables the clock divider. See Figure 23.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of PHASE resync. See the Phase Resync section for
more information. It also sets the timeout counter for fast lock.
See the Fast Lock Timer and Register Sequences section for
more information.
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REGISTER 4
Control Bits
With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed.
Figure 24 shows the input data format for programming this
register.
Feedback Select
DB23 selects the feedback from VCO output to the N-counter.
When this bit is set to 1, the signal is taken from the VCO directly.
When this bit is set to 0, it is taken from the output of the output
dividers. The dividers enable covering of the wide frequency band
(137.5 MHz to 4.4 GHz). When the divider is enabled and the
feedback signal is taken from the output, the RF output signals
of two separately configured PLLs are in phase. This is useful in
some applications where the positive interference of signals is
required to increase the power.
Divider Select
Bits[DB22:DB20] select the value of the output divider (see
Figure 24).
Mute-Till-Lock Detect
If DB10 is set to 1, the supply current to the RF output stage is shut
down until the part achieves lock as measured by the digital lock
detect circuitry.
RF Output Enable
DB5 enables or disables primary RF output, depending on the
chosen value.
Output Power
DB4 and DB3 set the value of the primary RF output power
level (see Figure 24).
REGISTER 5
Control Bits
With Bits[C3:C1] set to 1, 0, 1, Register 5 is programmed.
Figure 25 shows the input data form for programming this
register.
Lock Detect PIN Operation
Bits[DB23:DB22] set the operation of the lock detect pin (see
Figure 25).
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power up of the
of voltages to the supply pins:
•
•
•
•
•
•
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
ADF4150
after the correct application