ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 24

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4150
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the RF
pin back to the VCO, can result in reference spur levels as high
as −90 dBc. PCB layout needs to ensure adequate isolation
between VCO traces and the input reference to avoid a possible
feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
With dither off, the fractional spur pattern due to the quanti-
zation noise of the SDM also depends on the particular phase
word with which the modulator is seeded.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4150.
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
PHASE RESYNC
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
MOD is the fractional modulus. The phase resync feature in the
ADF4150
to the input reference. This is necessary in applications where the
output phase and frequency are important, such as digital beam
forming. See the Phase Programmability section for how to
program a specific RF output phase when using phase resync.
produces a consistent output phase offset with respect
IN
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Phase resync is enabled by setting Bit DB16, Bit DB15 in
Register 3 to 1, 0. When PHASE resync is enabled, an internal
timer generates sync signals at intervals of t
following formula:
where:
t
CLK_DIV_VALUE is the decimal value programmed in
Bits[DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits[DB14:DB3] of
Register 1 (R1).
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
a value that is at least as long as the worst-case lock time. This
guarantees that the PHASE resync occurs after the last cycle slip
in the PLL settling transient.
In the example shown in Figure 29, the PFD reference is 25 MHz
and MOD is 125 for a 200 kHz channel spacing. t
400 µs by programming CLK_DIV_VALUE to 80.
FREQUENCY
Phase Programmability
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD.
PFD
(INTERNAL)
is the PFD reference period.
PHASE
t
SYNC
SYNC
LE
–100
= CLK_DIV_VALUE × MOD × t
LAST CYCLE SLIP
0
Figure 29. Phase Resync Example
100
200
t
SYNC
INCORRECT PHASE
300
PLL SETTLES TO
SYNC
400
TIME (µs)
time is to be programmed to
500
600
PFD
SYNC
CORRECT PHASE
PLL SETTLES TO
AFTER RESYNC
700
given by the
SYNC
800
is set to
900
1000