ADF4150 AD [Analog Devices], ADF4150 Datasheet
ADF4150
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ADF4150 Summary of contents
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... VCO parts and is is available × package. R SET MULTIPLEXER FL SWITCH O CHARGE PUMP OUTPUT DIVIDE-BY-1/ STAGE -2/-4/-8/-16 RF MULTIPLEXER INPUT ADF4150 CP SD GND GND ©2011 Analog Devices, Inc. All rights reserved. MUXOUT OUT RF + OUT RF – OUT ...
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... ADF4150 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Circuit Description ......................................................................... 11 Reference Input Section ............................................................. Divider ............................................................................... 11 INT, FRAC, MOD, and R Counter Relationship.................... 11 INT N Mode ...
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... RF input power ≤ +5 dBm −10 dBm ≤ RF input power ≤ +5 dBm R = 5.1 kΩ SET 0.5 V ≤ V ≤ V − 0 0.5 V ≤ V ≤ V − 0 CMOS output chosen I = 500 µA OL Each output divide by two consumes output stage is programmable ADF4150 ...
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... The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution frequency (F and at a frequency offset (f) is given 10log(10 kHz/f) + 20log(F 1_f 6 Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer. B Version Min Typ Max Unit 31 ...
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... Rev Page unless otherwise noted. Operating A MIN MAX Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width DB1 DB0 (LSB) (CONTROL BIT C1 ADF4150 ...
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... ADF4150 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND Digital I/O Voltage to GND 1 Analog I/O Voltage to GND 1 REF to GND IN Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θ Thermal Impedance JA (Paddle-Soldered) ...
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... The output of the loop filter CP to drive the external VCO. TUNE must have the same value and must have the same value Rev Page ADF4150 . In systems where OUT . Place decoupling capacitors to the ground ...
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... ADF4150 Pin No. Mnemonic Description 22 SDV Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage Decoupling capacitors to the ground plane are to be placed as close as possible to this pin Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator. ...
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... Rev Page –60 –80 1k 10k 100k 1M FREQUENCY (Hz) = 100 MHz, PFD = 25 MHz, Loop Filter IN Bandwidth= 50 kHz –60 –80 1M 10M 100M 1G FREQUENCY (Hz) = 100 MHz, PFD = 25 MHz, Loop Filter IN 1k 10k 100k 1M FREQUENCY (Hz) = 100 MHz, PFD = 25 MHz, Loop Filter IN ADF4150 10M 10G 10M ...
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... ADF4150 –60 –80 –100 –120 –140 –160 –180 1k 10k 100k FREQUENCY (Hz) Figure 10. RF Output Phase Noise RF Dividers Used; Integer-N; Low Noise Mode; VCOOUT = 1750 MHz, REF = 100 MHz, PFD = 25 MHz, Loop Filter IN Bandwidth = 50 kHz –60 –80 –100 –120 –140 –160 –180 ...
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... HIGH –IN Rev Page DIVIDER N = INT + FRAC/MOD FROM N COUNTER THIRD ORDER FRACTIONAL INTERPOLATOR INT MOD FRAC REG REG VALUE Figure 15. RF INT Divider CLR1 CHARGE DELAY U3 PUMP CLR2 DOWN Figure 16. PFD Simplified Schematic ADF4150 TO PFD CP ...
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... Register 5 (R5) PROGRAM MODES allows the user Figure 20 through Figure 25 show how the program modes are to be set up in the ADF4150. A number of settings in the These include the modulus value, phase value, R counter value, reference doubler, reference divide-by-2, and current setting. This means that two events have to occur before the part uses a new value of any of the double-buffered settings ...
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... OUTPUT RESERVED POWER DB2 BS1 C3(1) C2(0) C1(0) RESERVED DB2 C3(1) C2(0) C1(1) ADF4150 CONTROL BITS DB1 DB0 CONTROL BITS DB1 DB0 CONTROL BITS DB1 DB0 CONTROL BITS DB1 DB0 CONTROL BITS DB1 DB0 CONTROL BITS DB1 DB0 ...
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... ADF4150 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 N16 N15 N14 N13 N12 N11 N10 N9 N16 N15 ...
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... LDF 0 FRAC INT (mA LDP THREE-STATE CP1 4.7kΩ 0 10ns 0 DISABLED 0 0.31 1 6ns 1 0.63 1 ENABLED 0 0.94 1 1.25 U3 POWER-DOWN U4 PD POLARITY 0 1.56 0 DISABLED 0 NEGATIVE 1 1.88 1 ENABLED 1 POSITIVE 0 2.19 1 2.50 0 2.81 1 3.13 0 3.44 1 3.75 0 4.06 1 4.38 0 4.69 1 5.00 ADF4150 CONTROL BITS DB1 DB0 C3(0) C2(1) C1(0) COUNTER RESET DISABLED ENABLED ...
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... ADF4150 RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 ...
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... D15 LOCK DETECT PIN OPERATION 0 0 LOW 0 1 DIGITAL LOCK DETECT 1 0 LOW 1 1 HIGH RESERVED RESERVED D14 Figure 25. Register 5 (R5) Rev Page ADF4150 CONTROL BITS DB2 DB1 DB0 0 C3(1) C2(0) C1(1) ...
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... MIN MIN In the ADF4150 Register 1 sets the prescaler values. 12-Bit Phase Value (Phase) These bits control what is loaded as the phase word. The word must be less than the MOD value programmed in Register 1. The word is used to program the RF output phase from 0° to 360° ...
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... DB4 puts the charge pump into three-state mode when programmed should be set to 0 for normal operation. Counter Reset DB3 is the R counter and N counter reset bit for the ADF4150. When this bit is 1, the RF synthesizer N counter and R counter are held in reset. For normal operation, this bit should be set to 0. ...
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... Figure 25 shows the input data form for programming this register. Lock Detect PIN Operation Bits[DB23:DB22] set the operation of the lock detect pin (see Figure 25). INITIALIZATION SEQUENCE The following sequence of registers is the correct sequence for initial power up of the ADF4150 of voltages to the supply pins: • Register 5 • Register 4 • Register 3 • ...
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... GSM 1800 standards, the programmable modulus is a (5) great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. (6) Rev Page available and the channel resolution (f IN ADF4150 ADF4150 ) required at RES IN ) RES allows the ...
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... ADF4150 This continues until the ADF4150 has gone past the desired frequency. The extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth ...
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... L is the repeat length of the code sequence PFD in the digital Σ-Δ modulator. For the third-order modulator used in the ADF4150, the repeat length depends on the value of MOD, as listed in Table 6. Table 6. Fractional Spurs with Dither Off Condition (Dither Off) ...
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... Thus, a look-up table of phase values corresponding to each frequency can be constructed for use when programming the ADF4150 look-up table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency. ...
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... LO in this configuration is 0.61°rms. The ADL5375 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4150, which allows levels from −4 dBm to +5 dBm from each output. The RF output is designed to drive a 50 Ω load but must be ac-coupled, as shown in Figure 30 ...
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... If vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter between 0.3 mm and 0.33 mm, and the via barrel plated with one ounce copper to plug the via. Rev Page ADF4150 ADF4150 SCLK CLK MOSI ...
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... ADF4150 Band 1 (2110 MHz to 2170 MHz). The maximum output power in that case is about 7 dBm. Both single-ended architectures can be examined using the EVAL-ADF4150EB1Z evaluation board. If differential outputs are not needed, the unused output can be 50Ω terminated or combined with both outputs using a balun. ...
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... INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADF4150BCPZ −40°C to +85°C ADF4150BCPZ-RL7 −40°C to +85°C EVAL-ADF4150EB1Z RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 4.10 0.30 4.00 SQ 0.25 3.90 0.18 19 0.50 18 ...