ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 26

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4150
INTERFACING
The
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 32 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register address table.
ADuC812 Interface
Figure 31 shows the interface between the
ADuC812
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the
32-bit word, which is accomplished by writing four 8-bit bytes
from the MicroConverter to the device. When the fourth byte
has been written, the LE input should be brought high to
complete the transfer.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as
lock detect and polled by the port input). When operating in
the described mode, the maximum SCLOCK rate of the
ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 125 kHz.
ADF4150
ADuC812
I/O PORTS
MicroConverter®. Because the ADuC812 is based
SCLOCK
has a simple SPI-compatible serial interface
Figure 31. ADuC812 to
MOSI
ADF4150
SDATA
CLK
LE
CE
MUXOUT
(LOCK DETECT)
Interface
ADF4150
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and the
needs a
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ADSP-21xx Interface
Figure 32 shows the interface between the
ADSP-21xx digital signal processor. The
32-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire
block of serial data before an interrupt is generated.
Set up the word length for 8 bits and use four memory locations
for each 32-bit word. To program each 32-bit latch, store the 8-bit
bytes, enable the autobuffered mode, and write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24-7) are rectangular.
The PCB pad for these is to be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land is to be centered on the pad. This ensures the solder
joint size is maximized. The bottom of the chip scale package
has a central thermal pad.
The thermal pad on the PCB is to be at least as large as the
exposed pad. On the PCB, there is to be a minimum clearance
of 0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
are to be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter is to be between 0.3 mm and 0.33 mm, and the
via barrel is to be plated with one ounce copper to plug the via.
ADSP-21xx
I/O PORTS
Figure 32. ADSP-21xx to
SCLK
MOSI
TFS
ADF4150
SDATA
CLK
CE
MUXOUT
(LOCK DETECT)
LE
ADF4150
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Interface
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needs a
and a