ADF4351BCPZ AD [Analog Devices], ADF4351BCPZ Datasheet
ADF4351BCPZ
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ADF4351BCPZ Summary of contents
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Data Sheet FEATURES Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output Typical jitter: 0.3 ps rms Typical EVM at 2.1 GHz: 0.4% Power supply: 3 3.6 ...
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ADF4351 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 Thermal ...
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Data Sheet SPECIFICATIONS SDV = V = 3.3 V ± 10%; AGND = DGND = VCO DD P temperature range is −40°C to +85°C. Table 1. Parameter REF CHARACTERISTICS ...
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ADF4351 Parameter 3 Minimum RF Output Power Maximum RF Output Power 3 Output Power Variation Minimum VCO Tuning Voltage Maximum VCO Tuning Voltage NOISE CHARACTERISTICS VCO Phase Noise Performance Normalized Phase Noise Floor ( SYNTH 5 Normalized 1/f ...
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Data Sheet TIMING CHARACTERISTICS SDV = V = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used VCO DD P otherwise noted. ...
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ADF4351 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating GND −0 +3 −0 +0 GND −0.3 ...
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Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance ...
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ADF4351 Pin No. Mnemonic Description 22 R Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage SET bias at the 25.5/R CP where 5.1 kΩ. SET I ...
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Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz –40 –50 –60 –70 –80 –90 –100 –110 –120 ...
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ADF4351 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k FREQUENCY (Hz) Figure 10. Fractional-N Spur Performance, Low Noise Mode, W-CDMA Band 2111.28 MHz, REF = 122.88 MHz, PFD = 30.72 MHz, Output ...
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Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. The SW1 and SW2 switches are normally closed. The SW3 switch is normally open. When power-down is initiated, SW3 is closed, and SW1 and ...
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ADF4351 MUXOUT AND LOCK DETECT The multiplexer output on the ADF4351 various internal points on the chip. The state of MUXOUT is controlled by the M3, M2, and M1 bits in Register 2 (see Figure 26). Figure 19 shows the ...
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Data Sheet The R counter output is used as the clock for the band select logic. A programmable divider is provided at the R counter output to allow division by an integer from 1 to 255; the divider value is ...
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ADF4351 REGISTER MAPS 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 ...
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Data Sheet 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 N16 N15 N14 N13 N12 ...
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ADF4351 LOW NOISE AND LOW SPUR MUXOUT MODES DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 ...
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Data Sheet RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 ...
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ADF4351 REGISTER 0 Control Bits When Bits[C3:C1] are set to 000, Register 0 is programmed. Figure 24 shows the input data format for programming this register. 16-Bit Integer Value (INT) The 16 INT bits (Bits[DB30:DB15]) set the INT value, which ...
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Data Sheet Reference Doubler Setting the DB25 bit to 0 disables the doubler and feeds the REF signal directly into the 10-bit R counter. Setting this bit to 1 multi- plies the REF frequency by a factor of 2 before ...
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ADF4351 Charge Cancelation Setting the DB21 bit to 1 enables charge pump charge cancel- ation. This has the effect of reducing PFD spurs in integer-N mode. In fractional-N mode, this bit should be set to 0. CSR Enable Setting the ...
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Data Sheet RF SYNTHESIZER—A WORKED EXAMPLE The following equations are used to program the synthesizer [INT + (FRAC/MOD)] × (f OUT where the RF frequency output. OUT INT is the integer division factor. FRAC is the ...
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ADF4351 It is important that the PFD frequency remain constant (in this example, 13 MHz). This allows the user to design one loop filter for both setups without encountering stability issues. Note that the ratio of the RF frequency to ...
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Data Sheet FAST LOCK LOOP FILTER TOPOLOGY To use fast lock mode, the damping resistor in the loop filter is reduced to one-fourth its value while in wide bandwidth mode. To achieve the wider loop filter bandwidth, the charge pump ...
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ADF4351 SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION With dither off, the fractional spur pattern due to the quantiza- tion noise of the Σ-Δ modulator also depends on the particular phase word with which the modulator is seeded. The phase word ...
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Data Sheet APPLICATIONS INFORMATION DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 34 shows how Analog Devices, Inc., parts can be used to implement such a system. Figure 34 shows the AD9788 ...
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ADF4351 INTERFACING TO THE ADuC70xx THE ADSP-BF527 The ADF4351 has a simple SPI-compatible serial interface for writing to the device. The CLK, DATA, and LE pins control the data transfer. When LE goes high, the 32 bits that were clocked ...
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Data Sheet OUTPUT MATCHING For optimum operation, the output of the matched in a number of ways; the most basic method is to con- nect a 50 Ω resistor bypass capacitor of 100 pF is ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADF4351BCPZ −40°C to +85°C ADF4351BCPZ-RL7 −40°C to +85°C EVAL-ADF4351EB1Z RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 BSC SQ 0.60 MAX 24 0 ...