ADF4150 AD [Analog Devices], ADF4150 Datasheet - Page 11

• Manufacturer Part Number: ADF4150
• Description: Fractional-N/Integer-N PLL Synthesizer
• Manufacturer: AD [Analog Devices]

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Division ratio is determined by INT, FRAC, and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the R
counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more informa-
tion. The RF VCO frequency (RF
where:
RF
oscillator (VCO).
INT is the preset divide ratio of the binary 16–bit counter
(23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
where:
REF
D is the REF
T is the REF
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
OUT
IN
RF
f
PFD
is the output frequency of external voltage controlled
is the reference input frequency.
OUT
= REF
REF
= f
IN
IN
IN
PFD
divide-by-2 bit (0 or 1).
IN
doubler bit.
NC
× (INT + (FRAC/MOD))
× [(1 + D)/(R × (1 + T))]
POWER-DOWN
SW1
Figure 14. Reference Input Stage
CONTROL
NO
NC
SW3
SW2
100kΩ
OUT
BUFFER
) equation is
TO R COUNTER
IN
pin
Rev. 0 | Page 11 of 28
(1)
(2)
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
Additionally, lower phase noise is possible if the anti-backlash
pulse width is reduced to 3 ns. This mode is not valid for
fractional-N applications.
R COUNTER
The 10–bit R counter allows the input reference frequency
(REF
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter and produces an output proportional to
the phase and frequency difference between them. Figure 16 is
a simplified schematic of the phase frequency detector. The
PFD includes a programmable delay element that sets the width
of the antibacklash pulse, which can be either 6 ns (default, for
fractional-N applications) or 3 ns (for integer-N mode). This
pulse ensures there is no dead zone in the PFD transfer function,
and gives a consistent reference spur level.
OUTPUT DIVIDERS
+IN
–IN
VCO OUTPUT/
HIGH
HIGH
IN
) to be divided down to produce the reference clock
FROM
D2
D1
CLR1
CLR2
U1
U2
RF N DIVIDER
Figure 16. PFD Simplified Schematic
Q1
Q2
N COUNTER
UP
DOWN
REG
Figure 15. RF INT Divider
INT
DELAY
U3
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD ORDER
FRACTIONAL
CHARGE
PUMP
VALUE
FRAC
ADF4150
TO PFD
CP