lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 98

• Manufacturer Part Number: lrs1386
• Description: Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

4.16.4 WAIT# Configuration
The WAIT# configuration bit RCR.8 (see Table 14)
controls the WAIT# output signal. This output signal can
be set to be asserted during or one CLK cycle before an
output delay occurs, when the burst read crosses the first
64-word boundary in continuous burst length or the 4- or
8-word burst length with no-wrap mode. Its setting will
depend on the system and CPU characteristic.
4.16.5 Burst Sequence
The burst sequence bit RCR.7 (see Table 14) determines
the order in which data is addressed in synchronous burst
mode. This order is configurable to either linear or Intel
burst order. The continuous burst length only supports
linear burst order. The order will be determined by the
CPU characteristic. Refer to Table 16 for linear burst
order and Intel burst order in detail.
4.16.6 Clock Configuration
The clock configuration bit RCR.6 (see Table 14)
configures the device to start a burst cycle, output data,
and assert WAIT# on the rising or falling edge of the
clock. This CLK flexibility enables interfacing the
LH28F320BX/LH28F640BX series Flash memory to a
wide range of burst CPUs.
4.16.7 Burst Wrap
The burst wrap bit RCR.3 (see Table 14) determines the
wrap mode as follows.
No-wrap mode (RCR.3="1") enables WAIT# to hold off
the system processor, as it does in the continuous burst
mode. In the no-wrap mode, the device operates similar to
continuous linear burst mode but consumes less power
during 4- and 8-word bursts. Refer to Table 16 for burst
wrap in detail.
• 4- or 8-word burst-accesses are performed within the
• 4- or 8-word and continuous burst-accesses cross the
burst-length boundary in wrap mode (RCR.3="0").
burst-length boundaries in no-wrap mode
(RCR.3="1").
No-wrap mode is only valid for linear burst order
(RCR.7="1").
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13302
FUM00701
Model No.: LRS1386
For example, if RCR.3="0" (wrap mode) and RCR.2-
0=001 (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1 and 3-0-1-2.
If RCR.3="1" (no-wrap mode) and RCR.2-0=001 (4-
word burst length), then possible linear burst sequences
are 0-1-2-3, 1-2-3-4, 2-3-4-5 and 3-4-5-6. No-wrap mode
not only enables limited non-aligned sequential burst, but
also reduces power by minimizing the number of internal
read operations.
4.16.8 Burst Length
The burst length is the number of words that the device
will output. The read configuration register bits RCR.2-0
(see Table 14) set the burst length. The LH28F320BX/
LH28F640BX series supports burst lengths of four and
eight words. It also supports a continuous burst mode. In
continuous burst mode, the device will linearly output
data until the internal burst counter reaches the end of the
device's burst-able address space or a partition boundary.
Refer to Table 16 for burst length in detail.
4.16.8.1 Continuous Burst Length
In continuous burst mode or 4-, 8-word burst with no-
wrap (RCR.3="1") mode, the flash memory may cause an
output delay when the burst read crosses the first 64-word
boundary. It depends on the starting address whether an
output delay will occur or not. When the starting address
is aligned to a 64-word boundary, the delay will not occur.
If the starting address is the end of a 64-word boundary,
the output delay will be equal to the frequency
configuration setting; this is the worst case delay. The
delay will only take place once during a continuous burst
access. If the burst read never crosses a 64-word
boundary, the delay will never happen. The WAIT#
output pin is used in continuous burst mode or 4-, 8-word
burst with no-wrap mode to inform the system if this
output delay occurs.
March 2, 2001
Rev. 2.20
52