lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 95

• Manufacturer Part Number: lrs1386
• Description: Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

4.16 Set Read Configuration Register
The Read Configuration Register (RCR) bits are set by
writing the Set Read Configuration Register command to
the device.
This operation is initiated by a two-cycle command
sequence. The read configuration register can be
configured by writing the command with the read
configuration register code. At the first cycle, command
(60H) and a read configuration register code is written. At
the second cycle, command (03H) and the same address
as the first cycle is written. The read configuration
register code is placed on the address bus, A
latched on the rising edge of ADV#, CE#, or WE#
(whichever occurs first). The read configuration register
code sets the device’s read configuration, burst order,
frequency configuration, and burst length. This command
functions independently of the V
be at V
returns to read array mode. The read configuration
register bits RCR.13-11, RCR.9, RCR.8, RCR.7, RCR.6,
RCR.3 and RCR.2-0 are only valid for synchronous burst
mode. Figure 16 shows set read configuration register
flowchart.
Command
IH
. After executing this command, the partition
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13302
PP
voltage. RST# must
Figure 14. Frequency Configuration
15
- A
0
, and is
FUM00701
Model No.: LRS1386
NOTES:
4.16.1 Device Read Configuration
Each partition supports a high performance synchronous
burst mode read configuration. The read configuration
register bit RCR.15 sets the device read configuration
(read mode; see Table 14).
All the parameter and main blocks support asynchronous
read mode, asynchronous 8-word page mode and
synchronous burst mode configuration.
Status register, query code, identifier codes, OTP block
and configuration register codes can only be read in
single asynchronous or single synchronous read mode.
• The read configuration register code can be read via
• All the bits in the read configuration register are set to
the Read Identifier Codes/OTP command (90H).
Address 0005H on A
configuration register code (see Table 6 through Table
8).
"1" after device power-up or reset.
(Read configuration register bits are volatile.)
(Read Mode)
March 2, 2001
15
- A
0
contains the read
Rev. 2.20
49